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32-bit embedded microprocessor adopting double instruction set

A microprocessor and embedded technology, applied in the direction of concurrent instruction execution, machine execution device, etc., can solve the problems of slow execution speed and unrealistic, and achieve the effect of improving efficiency, increasing area and improving performance.

Inactive Publication Date: 2003-10-22
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patented describes an improved system that solves problems with communication between different parts within one computer chip called J Card (JavaCard). It allows faster processing while avoiding collisions caused when multiple commands require access at once or wait until they get done before being able to start working on their own code. By connecting this quicker interface to the main memory's data paths instead of just sending them all over again, these systems have more efficient operations overall. They allow for better utilization of CPU cycles through caching techniques like register files and prefetch buffers. Overall, this innovation enhances how software works effectively across various types of computers.

Problems solved by technology

This patented technical problem addressed in this patents relates to developing enhanced functionality into mobile devices like tablets and servers through embedding computer cores called “J” Codes". These codes provide powerful computing capabilities without requiring expensive external components like memrists or logic gates. However, existing designs require significant CPU power consumption even when implementing Java code. Therefore, the challenge lies within the industry's focus towards reducing energy usage during operation.

Method used

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  • 32-bit embedded microprocessor adopting double instruction set
  • 32-bit embedded microprocessor adopting double instruction set
  • 32-bit embedded microprocessor adopting double instruction set

Examples

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Embodiment Construction

[0032] The present invention will be described in further detail below in conjunction with the accompanying drawings.

[0033] The five-stage pipeline structure of the RISC state and the six-stage pipeline structure of the Java state are shown in Figure 1 and figure 2 Shown. among them:

[0034] IF (instruction fetch), fetch the instruction from the instruction memory and lock it in the latch of the IF / ID stage. The RISC state is the same as the Java state at this level;

[0035] ID (instruction decoding), in the RISC state, the instruction latched in the IF / ID stage is taken out for decoding, and the control signal of the subsequent stage is generated. All the control signals are latched in the latch of the ID / EXE stage. The operand is read from the register file; in the Java state, the instruction length interception, instruction folding, and instruction decoding are performed to generate the control signal of the subsequent stage. All the control signals are locked in the latc...

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PUM

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Abstract

The invention is a kind of 32 bits embedded micro-processor which uses the new structure; it can process the local RISC instruction and Java virtual machine instruction. It is made up of instruction taking unit, instruction cache, instruction coding circuit, instruction replicating circuit, universal register group, data calculating unit, memory unit, promoting circuit and abnormity processing unit. The injunction cache and injunction replicating circuit is useful only in executing the Java virtual machine, at the same time, the universal register group is mapped into stack cache. The inventions have two instructions repertories, they can be switches seamlessly, but the circuit area increases only no more than 20% compared with the old.

Description

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Claims

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Application Information

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Owner FUDAN UNIV
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