32-bit embedded microprocessor adopting double instruction set
A microprocessor and embedded technology, applied in the direction of concurrent instruction execution, machine execution device, etc., can solve the problems of slow execution speed and unrealistic, and achieve the effect of improving efficiency, increasing area and improving performance.
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[0032] The present invention will be described in further detail below in conjunction with the accompanying drawings.
[0033] The five-stage pipeline structure of the RISC state and the six-stage pipeline structure of the Java state are shown in Figure 1 and figure 2 Shown. among them:
[0034] IF (instruction fetch), fetch the instruction from the instruction memory and lock it in the latch of the IF / ID stage. The RISC state is the same as the Java state at this level;
[0035] ID (instruction decoding), in the RISC state, the instruction latched in the IF / ID stage is taken out for decoding, and the control signal of the subsequent stage is generated. All the control signals are latched in the latch of the ID / EXE stage. The operand is read from the register file; in the Java state, the instruction length interception, instruction folding, and instruction decoding are performed to generate the control signal of the subsequent stage. All the control signals are locked in the latc...
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