Method for monitoring overlaying alignment on wafer

Abstract

A method for monitoring overlay alignment on a wafer that includes identifying a target machine, identifying a target process, identifying a plurality of critical layers, obtaining a plurality of overlay data from at least one of designated registration patterns on the wafer as baseline data, providing a plurality of reference overlay data, correlating the plurality of the reference overlay data with the baseline data to obtain overlay error, comparing the overlay error with specifications of the target machine, accepting the baseline data when the overlay error is within the specifications, and performing overlay alignment monitoring with the baseline data.

Description

technical field [0001] The present invention relates to a semiconductor manufacturing process, and more particularly to a method of monitoring the accuracy of overlay alignment during photolithographic steps. Background technique [0002] In the semiconductor manufacturing process, a plurality of integrated circuits can be manufactured on a silicon wafer, and several semiconductor material layers with different patterns and circuit layouts will cover one another at a predetermined position. At various stages in the manufacturing process, a machine called a stepper is used to expose the photoresist with ultraviolet light through a mask or reticle, and to Transfer the circuit layout pattern onto the photoresist layer. The circuit layout pattern is transferred to the photoresist through the grating in a step-and-repeat manner. The grating moves a predetermined distance at a time, exposing the pattern to the photoresist and developing it. The grating is continuously moved to ...

AI Technical Summary

Problems solved by technology

Also, because the machines used to do the testing are themselves used to make the wafers, the relative accuracy of the testing is uncertain

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