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Semiconductor storage device

A storage device and semiconductor technology, which is applied in the direction of semiconductor devices, information storage, static memory, etc., can solve the problems of low manufacturing yield of semiconductor storage devices and inability to remedy storage units, etc.

Inactive Publication Date: 2004-05-12
RENESAS TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this case, the second conventional technique cannot remedy all memory cells 120 on the row
Therefore, there is a problem that the manufacturing yield of the semiconductor memory device is not high.

Method used

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  • Semiconductor storage device
  • Semiconductor storage device
  • Semiconductor storage device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0110] 1 to 11 are schematic structural views of a semiconductor storage device 1 according to a first embodiment of the present invention. The semiconductor memory device 1 of the first embodiment is a 256 kbit RAM of an 8-bit x 32 k-word structure.

[0111] As shown in Figure 1, the semiconductor storage device 1 of the first embodiment comprises: a control part 4; the storage device is a standard RAM2; the redundant circuit function of the standard RAM2 is played by the control of the control part 4, and the same as the standard RAM2 is a storage device redundant RAM3. The standard RAM2 is a 256kbit RAM with an 8bit×32kword structure. In addition, the redundant RAM 3 is provided independently from the standard RAM 2 and is a 10 kbit RAM having a structure of 8 bits×1.25k words.

[0112] In the semiconductor storage device 1 of the first embodiment, a clock CLK, a 15-bit address A, a chip enable signal CEC, a write signal WEC, and an 8-bit data DI. Furthermore, the semico...

no. 2 example

[0259] 18-24 are schematic structural diagrams of a semiconductor storage device 21 according to a second embodiment of the present invention. The semiconductor memory device 21 of the second embodiment is a 256 kbit RAM of 8 bits x 32 k words structure.

[0260] As shown in FIG. 18, in the semiconductor memory device 21 of the second embodiment, in the structure of the semiconductor memory device 1 of the first embodiment described above, a control part 23 is used instead of the control part 4, and a redundant RAM22 is used instead of the redundant RAM3. The redundant RAM 22 has the same capacity as the redundant RAM 3, but when the structure switching signal OC (Organization Change) described later is "0", it becomes a 10kbit RAM with an 8-bit x 1.25k word structure, and when the structure switching signal OC is "0", When 1", it becomes a 10kbit RAM with a structure of 2 bits x 5k words. In addition, the redundant RAM 22 is provided with a redundant memory cell array co...

no. 3 example

[0325] 30-36 are schematic structural views of a semiconductor storage device 31 according to a third embodiment of the present invention. The semiconductor memory device 31 of the third embodiment is a 256 kbit RAM of 8 bits x 32 k words structure.

[0326] As shown in FIG. 30, structurally, the semiconductor storage device 31 of the third embodiment, in the semiconductor storage device 21 of the above-mentioned second embodiment, uses a control section 33 instead of the control section 23, and uses a redundant RAM 32 instead of the redundant RAM 22. . The redundant RAM 32 is a 6 kbit RAM having a structure of 2 bits×3k words, and includes a redundant memory cell array composed of a plurality of redundant memory cells arranged in 384 rows×16 columns. Furthermore, the redundant RAM 32 is provided independently of the standard RAM 2, and its operation is the same as that of the redundant RAM 22 of the second embodiment when the configuration switching signal OC=1, that is,...

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Abstract

Provided is a technique to improve the manufacturing yield of a semiconductor memory device which comprises a redundancy circuit. A semiconductor memory device (1) comprises a normal RAM (2) and a redundancy RAM (3) provided independently from the normal RAM (2), serving as a redundancy circuit, and a control unit (4) for replacing a normal memory cell array of the normal RAM (2) by a redundancy memory cell array of the redundancy RAM (3). The control unit (4) can replace the normal memory cell array by some of a plurality of redundancy memory cells constituting the redundancy memory cell array. Therefore, without using a redundancy memory cell which has a defect, a defective normal memory cell array can be replaced. As a result, a manufacturing yield of the semiconductor memory device (1) can be improved.

Description

technical field [0001] The present invention relates to a semiconductor memory device provided with redundant circuits. Background technique [0002] Fig. 66 is a circuit diagram showing the structure of a semiconductor memory device according to the first conventional art. As shown in FIG. 66 , the semiconductor memory device according to the first conventional technology includes a standard RAM (Random Access Memory) 101 having a structure of 3 bits×32 words and a redundant RAM 102 having a structure of 1 bit×32 words. The redundant RAM 102 is provided independently of the standard RAM 101 and functions as a redundant circuit of the standard RAM 101 . [0003] In standard RAM 101, 5-bit address AA<4:0> and write signal WE are input as address A<4:0> and write signal WE1, respectively, and 3-bit data DI<3:1> are input. In addition, the standard RAM 101 outputs 3-bit data DO<3:1>. [0004] On redundant RAM 102, 5-bit address AA<4:0> is input ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/04G11C29/00
CPCG11C29/808
Inventor 筱原寻史
Owner RENESAS TECH CORP