Pretaking mechanism for intenting to proceed storage

Abstract

A microprocessor apparatus is provided that enables exclusive prefetch of a cache line from memory. The apparatus includes translation logic and execution logic. The translation logic translates an extended prefetch instruction into a micro instruction sequence that directs a microprocessor to prefetch a cache line in an exclusive state. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues a transaction over a memory bus that requests the cache line in the exclusive state.

Description

technical field [0001] The present invention relates to the field of microelectronics, and in particular to a device and a method that enable a programmer to command a microprocessor to prefetch a cache line (cache line) in an exclusive MESI (modify, exclusive, share, invalid) state ) to its internal cache. Background technique [0002] In today's microprocessors, the data transmission speed between its internal logic blocks far exceeds its access speed with external memory. In an x86 desktop computer configuration, the interface between the bus and system memory runs at hundreds of megahertz (megahertz) speeds, but the internal microprocessor clock speed is approaching gigahertz (gigahertz) . Therefore, in recent years, a hierarchical body of cache structures has been developed, which makes it unnecessary for high-performance microprocessors to read or write data in a slow memory bus (memory bus) every time. bus) to perform operations (transaction), and to better play it...

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Problems solved by technology

But the prefetch instructions do not operate on the operands of the program flow

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