Duty-cycle-efficent SRAM cell test

Abstract

A method and structure for the invention includes an integrated memory structure having a built-in test portion. The integrated memory structure has memory cells, bitlines and wordlines connected to the memory cells, wordline decoders connected to a plurality of the wordlines, bitline restore devices connected to the bitlines for charging the bitlines during read and write operations, and a clock circuit connected to the wordlines. During a test mode the wordline decoders simultaneously select multiple wordlines that the bitline restore devices maintain in an active state and the clock circuit maintains the multiple wordlines and the bitline restore devices in an active state for a period in excess of a normal read cycle. The invention also includes transistors which are connected to the memory cells. The transistors include bitline contacts which are stressed during the test mode.

Description

technical field

[0001] The present invention relates generally to the testing of semiconductor memory cells, and in particular to improved methods and structures for stressing and testing contacts within semiconductor structures. Background technique

[0002] A typical semiconductor static random access memory (SRAM) device includes a plurality of word lines, a pair of bit lines and memory cells, wherein cell latches and pass devices are connected between the word lines and the pair of bit lines the intersection between. The pass devices of the memory cells are connected to the pair of bit lines through bit line contacts. These bit line contacts allow the contents of the memory cell to be successfully read from and written to the cell latch during a read or write operation. A bitline contact with too much resistance (resistive bitline contact) will not properly allow reading or writing of the memory cell. Resistive bitline contacts can occur as a result of mechanical fail...

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