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Bit likelihood calculation method and demodulation device

A calculation method, a likelihood technique, applied in phase-modulated carrier systems, other decoding techniques, shaping networks in transmitters/receivers, etc., and can solve problems such as hindering bit likelihood

Inactive Publication Date: 2004-08-18
PANASONIC CORP
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Problems solved by technology

[0003] However, when a multi-value modulated signal is demodulated by Viterbi equalization such as MLSE, a symbol-based transmission signal string is output, and the signal is not output as bits that can be mapped in phase space. This method prevents the use of the above methods to compute bit likelihoods

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  • Bit likelihood calculation method and demodulation device

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no. 1 Embodiment

[0012] First, Viterbi equalization considering a signal delayed by only one unit time (for example, 1 symbol time) requiring constraints is explained. In realizing Viterbi equalization, a prefilter is often provided to prevent deterioration caused by timing jitter or the like. Here, when prefilter taps (taps) and replica taps (replica taps) of Viterbi equalization are determined according to the MMSE (Minimum Mean Sequence Estimator) standard, all taps become "0 ". To avoid this, the tap of the previous signal corresponding to the replica tap is fixed to 1 as a constraint. When such Viterbi equalization is used, the present invention relates to a bit likelihood calculation method.

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0014] figure 1 A block diagram showing the structure of a demodulation device according to an embodiment of the present invention.

[0015] The pre-filter 101 ab...

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Abstract

The Viterbi calculation section 106 performs a Viterbi calculation by adding a branch metric to a path metric output from the metric selection section 105 and selecting a path having the smallest addition result and determines a surviving path having the smallest path metric and a second path having the second smallest path metric. The likelihood calculation section 107 compares each bit of the surviving path with the corresponding bit of the second path, sets lower likelihood for a bit having a different value than for a bit having the same value, and in this way calculates likelihood of each bit composing each symbol of the surviving path based on the relationship between the surviving path and the second path and further using mapping rules of the modulated signal. This makes it possible to calculate bit likelihood with a high degree of accuracy when demodulation is performed using Viterbi equalization to improve the error correcting capacity.

Description

technical field [0001] The present invention relates to a bit likelihood calculation method and a demodulation device, which calculates likelihood for each bit (bit) constituting a symbol. Background technique [0002] In Unexamined Japanese Patent Publication No. HEI 5-14213, one of conventional bit likelihood calculation methods in the demodulation process of a PSK modulated signal is described. In this method, a phase difference component from the origin and a distance error component are calculated from coordinate information in a demodulated phase space, and bit likelihoods are calculated using these components. [0003] However, when a multi-value modulated signal is demodulated by Viterbi equalization such as MLSE, a symbol-based transmission signal string is output, and the signal is not output as bits that can be mapped in phase space. This method prevents the calculation of bit likelihoods using the methods described above. Contents of the invention [0004] An...

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Application Information

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IPC IPC(8): G06F11/10H03M13/41H04L25/03H04L27/22
CPCH03M13/4138H03M13/6325H04L25/03318
Inventor 斋藤佳子上杉充
Owner PANASONIC CORP
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