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Method for resolving satisfiability problem of very large scale integrated circuit (VLSIC) verification

A large-scale integrated circuit, solution technology, applied in the direction of circuits, electrical components, electrical digital data processing, etc.

Inactive Publication Date: 2004-09-01
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
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Problems solved by technology

[0005] The purpose of the present invention is to propose a solution to the satisfiability problem of VLSI verification that can greatly reduce the number of decisions and improve work efficiency

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  • Method for resolving satisfiability problem of very large scale integrated circuit (VLSIC) verification
  • Method for resolving satisfiability problem of very large scale integrated circuit (VLSIC) verification
  • Method for resolving satisfiability problem of very large scale integrated circuit (VLSIC) verification

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Embodiment Construction

[0023]According to the present invention, the method for solving the satisfiability problem of VLSI verification includes five steps: decision process, Boolean constraint simplification process, backtracking process, learning process and reasoning process. According to this method, we design the corresponding algorithm program. The specific calculation steps are as follows:

[0024] 1. Scan the clauses of the original question and initialize the current values ​​of all variables;

[0025] 2. Select the variable with the largest current value as the decision variable this time, and assign a value according to the current value of the variable. For example, the variable x is a decision variable, and x has a higher current value than x', then let x=1, otherwise, let x=0; if it is found that all variables have been assigned in the process, it means that the original problem can be satisfied , output the assignment of the variable and exit.

[0026] 3. According to the assignmen...

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Abstract

The invention is a method for solving the satisfiability of grand scale integration test. It is based on depth priority search, adds in reasoning process, and uses the reasoning process to carry on correspondent improvement to tactics of decision. The steps include: decision making process, simplifying process of Boolean restrain, back-track process, studying process and reasoning process. Its data structure uses 2-3 mixed variable monitoring data structure. The invention can decrease the times of decision greatly, and upgrades the operating efficiency.

Description

technical field [0001] The invention belongs to the technical field of ultra-large-scale integrated circuits, and in particular relates to a solution to the satisfiability problem of ultra-large-scale integrated circuit verification. Background technique [0002] With the development of VLSI, circuits with millions or even tens of millions of gates can be integrated on a single chip. Designing such a circuit is a very complicated problem, and it is even more difficult to verify its correctness. Everyone knows that it costs tens of thousands to hundreds of thousands of dollars to do a chip trial. If it cannot be verified that it is 100% correct, as long as there are one or two wrong chips, trial production will be carried out, which will not only cause huge economic losses, but also bring loss of time to market. Therefore, the correctness of the large-scale integrated circuit chip after the design must be verified. Only when it is 100% correct can it be put into trial produ...

Claims

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Application Information

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IPC IPC(8): G06F17/50H01L21/66H01L21/82
Inventor 丁敏唐璞山
Owner FUDAN UNIV
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