Partial integrated compression tree generating method based on mixed compression structure

A hybrid compression and tree compression technology, which is applied in the calculation using number system representation and non-contact manufacturing equipment for calculation. cost, the effect of reducing the total delay

Inactive Publication Date: 2004-12-22
SHANGHAI JIAO TONG UNIV
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Problems solved by technology

However, using a 4:2 compressor does not guarantee the optimal delay characteristics of the partial product compression tree; and the partial product compression tree based on other compressors is not as good as the delay characteristic based on 3:2 compression due to the complexity of its circuit. Partial product compression tree of compressor or partial product compression tree based on 4:2 compressor

Method used

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  • Partial integrated compression tree generating method based on mixed compression structure
  • Partial integrated compression tree generating method based on mixed compression structure

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Embodiment

[0024] Implement an 8×8 multiplier and use a non-Booth coded Wallace-tree structure. At this time, the total number of columns of the partial product of the multiplier is 15, and the number of partial products to be compressed on each column is: 1, 2, 3 , 4, 5, 6, 7, 8, 7, 6, 5, 4, 3, 2, 1. Take the calculation of column 8 as an example:

[0025] Step 1: The current column number is 8, the current layer number is 1; the current column number is less than the total number of columns of the partial product of the multiplier, 15, and the next step is executed;

[0026] Step 2: The number of bits to be compressed currently is 12 and not less than 4, and a 4:2 compressor is used as the root of the entire partial product compression tree;

[0027] Step 3: The maximum number of signals that the current layer can accept is 5, the number of carry-reserved signals generated is 1, the number of carry-out signals is 1, the number of partial products to be compressed in the current column...

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Abstract

The invention relates to a partial product compressed tree generating method based on a mixed compressed structure, by combining the characters of a 3 to 2 compressor and a 4 to 2 compressor and from a growing point of view, constructing the partial product compressed tree. It takes a 4 to 2 compressor as a root of the compressed tree, grows two branches upward on the root or directly receives four partial product signals and a carry input signal. If it grows branches, it determines to adopt a 4 to 2 or 3 to 2 compressor according to the number of signals to be compressed, and if the number of signals able to be received by the two branches at most is less than that of signals to be compressed, these branches continuously grow branches at their respective compression ratios until the number of signals able to be received by the top braches is up to or beyond that of signals to be compressed. It reduces the time and area of the partial produce compressed tree, reduces the total time delay and area of the multiplication or MAC, and provides the possibility of heightening the frequency and performance of a digital signal processor and reducing the cost of a chip.

Description

technical field [0001] The invention relates to a method for generating a partial product compression tree based on a hybrid compression structure, which is used for the design of a high-speed multiplier or a high-speed multiply-add unit in a digital signal processor, and belongs to the technical field of digital signal processing. Background technique [0002] A multiplier or a multiply-add unit is a key arithmetic unit of various digital computing chips, especially a digital signal processing chip (DSP). Booth-coded Wallace-tree multipliers or non-Booth-coded Wallace-tree multipliers are the most representative of various widely used multiplier architectures. Multiplication can usually be divided into three steps: generate a partial product; compress the partial product to obtain two intermediate results; finally add the two intermediate results with an adder to obtain the final result. Partial product compression is the longest part of the whole multiplication operation....

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/52
Inventor 王田陈健
Owner SHANGHAI JIAO TONG UNIV
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