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Method and apparatus for interfacing a processor to a coprocessor

A coprocessor and processor technology, which is applied in register devices, machine execution devices, electrical digital data processing, etc., can solve problems such as uneconomical performance and price ratios

Inactive Publication Date: 2005-01-05
MOTOROLA INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Thus, for coprocessors, many otherwise attractive applications are not cost-effective for performance

Method used

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  • Method and apparatus for interfacing a processor to a coprocessor
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  • Method and apparatus for interfacing a processor to a coprocessor

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Embodiment Construction

[0040] In the following description, numerous specific details are employed, such as specific word or byte lengths, etc., in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention can be practiced without these specific details. In other instances, circuits are shown in block diagram form in order not to obscure the invention in unnecessary detail. For the most part, timing considerations and similar details have been omitted, since these details are not necessary for a complete understanding of the invention and are within the skill of those skilled in the relevant arts.

[0041] The term "bus" is used to refer to a number of signals or wires that can be used to convey one or more different types of information, such as data, address, control or status. The terms "assert" and "negate" are used to refer to a signal, state or description of a similar device as its logically true or l...

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PUM

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Abstract

A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

Description

[0001] The application for the present invention is a divisional application No. 98118581.9 filed on September 4, 1998, with the title of the invention "Method and device for interfacing a processor with a coprocessor". technical field [0002] The present invention relates to a data processing system having a processor and at least one coprocessor, and more particularly to a method and apparatus for interfacing a processor with a coprocessor. Background technique [0003] The ability to extend the functionality of a baseline architecture processor through dedicated and specialized hardware functional elements is an important aspect of scalable and scalable architectures. [0004] One of the preferred ways to extend the functionality of a base architecture processor is through the use of coprocessors. These coprocessors are usually dedicated, single-purpose processors that operate under the direction of the processor. A common use of coprocessors is as a math coprocessor, o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/40G06F9/30G06F9/38
CPCG06F9/3012G06F9/30116G06F9/3861G06F9/3879G06F9/3881G06F15/16
Inventor 威廉姆·C.·莫耶约翰·阿兰德斯杰夫里·W.·斯考特
Owner MOTOROLA INC