Semiconductor memory device and semiconductor integrated circuit device

Abstract

A row control circuit 100 of the semiconductor memory device is provided with an oscillator 110 as a clock oscillator for generating an internal clock, a D flipflop 181 as a refresh request signal RFRQ generation circuit for generating a refresh request signal RFRQ synchronously with the internal clock and a delay circuit 182, a NAND gate 184, an AND gate 182, a D flipflop 185, a delay circuit 188, an AND gate 189 and an OR gate 190 as refresh control circuits. By using a refresh request signal RFRQ and an active signal ACT, internal refresh is performed internally in a DRAM separately from an external refresh command. To provide a semiconductor memory device and a semiconductor integrated circuit device capable of simplifying the memory control while securing the sufficient refresh function.

Description

technical field [0001] The present invention relates to a semiconductor memory device and a semiconductor integrated circuit device including memory cells that need to be refreshed in order to hold data. Background technique [0002] DRAM requires a refresh operation in order to retain data in memory cells. In the DRAM disclosed in Patent Document 1, an auto-refresh operation of refreshing by an external refresh request signal and a self-refresh operation of refreshing by an internal timer by setting the DRAM to a self-refresh mode can be realized. [0003] In the case of automatic refresh, a refresh request signal must be generated externally and provided to the DRAM during the interval between read and write operations, so as to perform a given number of refresh operations at regular intervals. [0004] In the case of self-refresh, since the refresh operation of DRAM is started according to the internal timer, there is no need to generate timing signals for each refresh o...

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Problems solved by technology

However, the read and write action requests are continuous, and the number of NOP cycles is very small. Since a given number of refresh actions must be performed every certain cycle, if the required number of times is not reached, the data will not be maintained.

[0009] In the DRAM of Patent Document 3, even if the refresh operation is not performed from the outside, the data of the memory cell can be retained by an internal refresh operation inserted before the processing of the read and write operations, and even if the read and write access request does not carry a NOP Refresh operations can be performed accurately even in continuous situations, but if frequent read and write operations are performed, refresh operations will also become frequent, so power consumption will increase

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