Method and apparatus for handling reversion of primary and secondary clock systems

A technology for clock system and active-standby switching, which is applied in transmission systems, digital transmission systems, data exchange networks, etc., and can solve problems such as excessive clock phase difference and high bit error rate

Inactive Publication Date: 2005-08-17
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a method and device for processing the active/standby switchover of the clock system,

Method used

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  • Method and apparatus for handling reversion of primary and secondary clock systems
  • Method and apparatus for handling reversion of primary and secondary clock systems
  • Method and apparatus for handling reversion of primary and secondary clock systems

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Embodiment Construction

[0032] Below according to accompanying drawing and embodiment the present invention will be described in further detail:

[0033] figure 2It is a flow chart of the method for processing the active / standby switchover of the clock system in the present invention. First execute step 201 to loop back the crystal output of the main and standby clock systems to the input terminals of the clock selection circuits of the two clock systems through the backplane, and pay attention to the wiring of the backplane and the clock system so that the same crystal oscillator clock is looped back through the backplane. The wiring lengths passed by the input ends of the clock selection circuits of the two clock systems are the same; then execute step 202 to make the clock selection circuits on the active and standby clock systems select the crystal oscillator clock output on the active clock system, and execute step 203 to pass the lock The phase loop circuit locks the output of the clock select...

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Abstract

The invention discloses a method for processing active-standby switching of a clock system. The clock is used as the output; the output of the clock selection circuit is locked by the phase-locked loop circuit to obtain the output clocks of the main and standby clock systems; the output clocks are driven to each service single board point-to-point. Also disclosed is a device for processing active-standby switching of a clock system, which is characterized in that both the main and standby clock systems include a crystal oscillator, a clock selection circuit, a phase-locked loop circuit and a clock drive circuit. The invention solves the problems that the clock phase difference is too large and the bit error rate is high in the main and standby switching process.

Description

technical field [0001] The present invention relates to the field of communication and other electronic fields, in particular to a method and device for processing master-standby switchover of a clock system. Background technique [0002] At present, with the rapid development of broadband networks, users not only put forward high requirements for the content of network services, but also pay more and more attention to the quality of network services, which puts forward higher and higher requirements for the reliability of communication equipment. In order to improve the reliability of the system, the most commonly used method is to adopt the active and standby working mode for the core board. When the active core board fails, the business is transferred to the standby core board that can work normally through the active and standby switchover. With the improvement of users' requirements for network service quality, higher requirements must be placed on the bit error rate of...

Claims

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Application Information

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IPC IPC(8): H03L7/08H04B1/74H04L12/24
Inventor 徐劲松马德煦廖珺管燕萍
Owner ZTE CORP
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