AES add decipher circuit optimization method and multiplex sbox module

Abstract

This invention relates to an AES cipher / decipher circuit multiplex Sbox module including a negating circuit, a first gating switch, a second gating switch, a ciphered affine transformation circuit, a deciphered affine transformation circuit and a control unit, in which, the first gating switch is connected with the input of the negating circuit, the deciphered affine transformation circuit is connected with high order end 1, the second gating switch is connected with the output of the negating circuit. The ciphered affine transformation circuit is connected with low order end o of the second gating switch and the control unit controls the two switches to gate high order end 1 or low order end o simultaneously. Besides, this invention also provides an optimizing method for AES cipher / decipher circuits.

Description

technical field

[0001] The invention relates to encryption and decryption technology, in particular to the optimization of AES encryption and decryption circuits. Background technique

[0002] The AES algorithm is the abbreviation of Advanced Encrypt Standard, which is a block cipher algorithm published by the American National Standards Committee NIST. The length of the encryption key in the AES algorithm is 128, 192, and 256 bits. For specific applications, the length of the key is fixed. The AES algorithm has been widely discussed and recognized due to its advantages of wide application range, short waiting time, relatively easy to hide, and high throughput.

[0003] The strength of the AES algorithm is based on the inversion operation on the finite field with base 256. At the same time, for encryption and decryption, an affine transformation needs to be done after or before the inversion. In the hardware circuit, the general method is to add the inversion operation on ...

Images