Automatic fault-testing of logic blocks using internal at-speed logic-bist

Abstract

System and method for automatic fault-testing of a logic block and the interfaces of macros with logic gates inside a chip, using an at-speed logic-BIST internal to the chip. Following an initialization of internal storage elements, a set of test signals are generated and processed by the logic block. The output of the logic block is accumulated into a signature and compared to a reference signature to detect faults. Testing can be performed on an ATE (Automatic Test Equipment) using a simple test vector, or can be performed by a field engineer on the actual board comprising the chip.

Description

technical field [0001] The present invention relates generally to hardware testing, and more particularly to automated real-time failure testing of logic modules using logic-BIST (built-in self-test). Background technique [0002] Testing of digital logic modules is typically performed using automatic test equipment (ATE) and scan chains in the digital logic module. While this approach works, the speed at which this test is performed is slower than the digital logic block is expected to operate under the conditions under test. This way, logic that makes a mistake at real or desired speed but passes at low speed is not detected. Furthermore, such tests generally do not test the macro interface of digital logic. Therefore, since the interface between macros and logic is usually tested separately, connection failures may not be detected. Moreover, the complex ATE interface does not allow field engineers to test chips in the field for convenience. [0003] Therefore, there i...

AI Technical Summary

Problems solved by technology

Although this method works, this test executes at a slower rate than the digital logic block is expected to operate under the test conditions

This way, logic that goes wrong at real or desired speed but passes at low speed is not detected

Also, such tests generally do not test the macro-interfaces of digital logic

Therefore, since the interface between macros and logic is usually tested separately, connection failures may go undetected

Also, the complex ATE interface does not allow field engineers to test chips in the field for convenience

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