8 results about "Reference designator" patented technology

The invention provides a mask pattern generation method, a mask, a semiconductor structure and a manufacturing method thereof. The mask pattern generation method comprises the following steps: acquiring a mask pattern template comprising a cutting channel region and a reference mark pattern comprising a graphic pattern; the reference mark pattern is divided into a plurality of reference mark areas; extracting contours of partial graphic patterns in each reference mark area by using the auxiliary graphs to obtain a plurality of auxiliary mark patterns, and arranging the auxiliary mark patterns in the cutting channel area; and respectively intercepting a part of the graphic pattern in each reference mark area to obtain a plurality of local mark patterns, and arranging the local mark patterns at the positions of the corresponding auxiliary mark patterns in the cutting channel area to obtain a target mask pattern, the plurality of local mark patterns transferred to the semiconductor structure are combined into an alignment mark pattern matched with the graphic pattern in the cutting channel of the semiconductor structure. According to the embodiment of the invention, the alignment precision in the processing process of the packaging technology is improved.

The present invention provides a silicon carbide substrate, a silicon carbide single crystal substrate, and a method for manufacturing a silicon carbide semiconductor device that can accurately determine the quality of the device's active region. [Solution] The method for manufacturing a silicon carbide semiconductor device includes a silicon carbide single crystal substrate and a silicon carbide epitaxial film provided on the silicon carbide single crystal substrate, in which a reference mark serving as a reference for two-dimensional position coordinates is formed on the silicon carbide substrate, after the reference mark is formed, at least one of polishing or cleaning is performed on the reference mark formation surface of the silicon carbide substrate, the position coordinates of a defect in the silicon carbide substrate are identified based on the reference mark, an active element region is formed on the silicon carbide substrate, the position coordinates of the active element region are identified based on the reference mark, and the quality of the active element region is determined by relating the position coordinates of the defect and the position coordinates of the active element region.

This invention discloses a method for automatically generating reference schematics for electronic devices, an electronic device, and a storage medium. The method includes: extracting the set of actual chip models corresponding to the underlying physical point diagram of the electronic device; assigning uniformly standardized virtual standard reference designators to components in the chip model set based on a global standard mapping dictionary, and establishing a heterogeneous data mapping table; using the chip model set as the query key, initiating a batch search to a general circuit module library to retrieve matching general circuit data packages; dynamically replacing variable placeholders in the general circuit data packages with virtual standard reference designators based on the heterogeneous data mapping table; performing topological sorting on the replaced general circuit data packages according to classification weight values ​​using a topological sorting algorithm to generate a multi-page structured logic reference schematic set, and generating a dynamic directory with interactive jump anchors based on the multi-page structured logic reference schematic set. This method can solve the problem of low repair efficiency caused by the lack of original manufacturer circuit diagrams.

Techniques of item assembly testing that include: obtaining assembly information; generating, based on the assembly information, a bill of materials (BOM) including a listing of parts corresponding to a configuration of parts defined by the assembly information; generating, based on the listing of parts, a set of reference designators; obtaining an item label set; generating, based on the item label set and the set of reference designators, an assembly bill of materials (ABOM) that includes the labels associated with the parts reference designators; generating, for a test of the item assembly, a record of the ABOM; obtaining test data for parts of the item assembly (the item assembly tested having a configuration specified the ABOM); and generating a test results ABOM including test data for the parts associated with the labels for the reference designators associated with the parts.

The application provides a mask pattern generation method, a mask, a semiconductor structure and a manufacturing method thereof. The mask pattern generation method comprises: obtaining a mask pattern template comprising a scribe lane region and a reference mark pattern comprising a pattern; the reference mark pattern is divided into a plurality of reference mark regions; an outline of a part of the pattern in each reference mark region is extracted by using an auxiliary pattern to obtain a plurality of auxiliary mark patterns which are arranged in the scribe lane region; a part of the pattern in each reference mark region is cut respectively to obtain a plurality of local mark patterns which are arranged at positions of the corresponding auxiliary mark patterns in the scribe lane region to obtain a target mask pattern, so that the plurality of local mark patterns transferred to the semiconductor structure are combined into an alignment mark pattern matching the pattern in the scribe lane of the semiconductor structure. Through the embodiments of the application, the alignment accuracy in the packaging process is improved.

This invention discloses a method for tracing solder paste printing and component placement misalignment based on multi-source detection data fusion, belonging to the technical field of automatic inspection systems for printed circuit boards. It includes a data caching module that receives multi-source data, constructs a data pool, and establishes a reference designator-package type mapping; a rule engine module that extracts detection results, corrects thresholds based on package type, converts them into dimensionless risk coefficients, and distributes them to a decision tree for root cause decoupling analysis according to defect type; it categorizes by batch, standardizes root cause expressions, calculates weights and normalized proportions, and outputs dominant and secondary root causes; and generates and outputs a process report. This invention solves the technical problem of how to integrate multi-source data from solder paste printing inspection and component placement inspection, and adaptively corrects judgment thresholds for different package types to achieve accurate tracing of the root causes of placement misalignment defects and batch-level root cause statistics. The invention automatically outputs dominant and secondary root causes, providing a quantitative basis for closed-loop optimization of the production process.

A substrate bonding device (1) comprises a control unit (80) that acquires the state of inclination of at least one of a first stage (51) and a second stage (61) on the basis of the degree of focus of an overlap image (G) in which a first reference mark (MA1) and a second reference mark (MA2) imaged by a reference mark imaging unit (72) that images the first reference mark (MA1) and the second reference mark (MA2) overlap, the first reference mark (MA1) and the second reference mark (MA2) overlapping when viewed from the vertical direction.