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Adding-up apparatus and digital circuit unit of its direct digit frequency synthesizing apparatus

A technology of digital circuits and adding units, applied in the field of direct digital frequency synthesis, can solve problems such as the number of bits and operating frequency limitations, and achieve the effect of improving accuracy

Inactive Publication Date: 2006-10-25
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These two disadvantages cause the number of accumulated bits and operating frequency to remain limited

Method used

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  • Adding-up apparatus and digital circuit unit of its direct digit frequency synthesizing apparatus
  • Adding-up apparatus and digital circuit unit of its direct digit frequency synthesizing apparatus
  • Adding-up apparatus and digital circuit unit of its direct digit frequency synthesizing apparatus

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0064] Embodiment 1: frequency reduction accumulating device.

[0065] See Figure 5 , Figure 5 It is a schematic diagram of the down-frequency accumulating device in Embodiment 1 of the present invention. Figure 5The frequency reduction and accumulation device shown includes an increment multiplier unit 501 , an accumulator 502 , a delay circuit 503 , and an addition unit 504 . Wherein, the increment multiplier unit 501 includes k-1 multipliers and one M transmission line. Coefficients of the k-1 multipliers are 2, 3, 4...k respectively, and k is a natural number greater than 1. The multiplier and the M transmission line respectively receive the input delta M. Among them, the multiplier whose coefficient is less than or equal to k-1 multiplies the increment M and the coefficient, and generates the multiple value of the increment respectively: M×2, M×3..., M×(K-1) are respectively output to the addition unit 504 . The multiplier with a coefficient equal to k multiplies...

Embodiment 2

[0080] Embodiment 2: The output of the accumulation device is directly input to the digital circuit part of the high-speed DDS device of the phase-to-amplitude conversion circuit.

[0081] See Figure 6 , Figure 6 It is a partial schematic diagram of the digital circuit of the high-speed DDS device in Embodiment 2 of the present invention, which includes a down-frequency phase accumulation circuit 601 and a phase-to-amplitude conversion unit 602 . Down-frequency phase accumulation circuit 601 such as Figure 5 The accumulating device shown in the figure receives a phase increment M with a frequency of fc, and outputs a set of k-channels of phase data every k / fc time: P1, P2, ..., Pk.

[0082] The phase-to-amplitude conversion unit 602 includes k phase-to-amplitude conversion circuits 603, and each phase-to-amplitude conversion circuit 603 receives one of the k output phase data P1, P2, ..., Pk of the down-frequency accumulation circuit 601. Convert it in k / fc time. The ph...

Embodiment 3

[0084] Embodiment 3: The digital circuit part of a high-speed DDS device including a frequency adjustment circuit.

[0085] See Figure 7 , Figure 7 It is a partial schematic diagram of the digital circuit of the high-speed DDS device in Embodiment 3 of the present invention, which includes a down-frequency phase accumulation circuit 701 , a frequency adjustment circuit 702 , and a phase-to-amplitude conversion unit 703 . Down-frequency phase accumulation circuit 701 such as Figure 5 The accumulating device shown receives a phase increment M with a frequency of fc, and outputs a set of k-channel phase data every k / fc time: P1, P2, ..., Pk.

[0086] The frequency adjustment circuit 702 is arranged between the down-frequency phase accumulating circuit 701 and the phase-to-amplitude conversion unit 703, receives a group of k-channel phase data output by the down-frequency phase accumulating circuit 701, outputs a group of i-channel phase data, and sends them to a The phase-t...

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Abstract

This invention discloses an accumulation device including an increment multiple unit, which receives incremental data input from outside to generate the multiple incremental values of K of 1-K times increments, an accumulator receiving k-times of incremental values output by the increment multiple unit to generate an accumulated value to be output to an addition unit and taken as one circuit of phase data to be output, an addition unit receiving the accumulated value output by the accumulator and 1-k-1 times of increment value output by the increment multiple unit to add the accumulated result and the 1-k-1 times of value to generate the sum of k-1 to be taken as the k-1 phase data to be output, in which, k is a natural number greater than 1. This invention also discloses a digital circuit unit for a direct digital frequency composition device utilizing said accumulating device for phase accumulation.

Description

technical field [0001] The present invention relates to the technology of direct digital frequency synthesis, in particular to the accumulating device which can be applied to the direct digital frequency synthesis device and the digital circuit unit of the direct digital frequency synthesis device. Background technique [0002] Direct Digital Frequency Synthesis DDFS (Direct Digital Frequency Synthesis) is generally referred to as Direct Digital Synthesis DDS (Direct Digital Synthesis), which is a technology used to generate various frequency clocks. [0003] See figure 1 , figure 1 It is a schematic diagram of the principle of the DDS device in the prior art. figure 1 The DDS device includes a phase accumulation circuit 101, a phase-to-amplitude conversion circuit 102, a digital-to-analog conversion circuit (DAC) 103, a filter / amplification circuit 104, etc., receiving a phase increment M and outputting a sine wave or a square wave. The work of all digital circuits requi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03B28/00
Inventor 李波赵猛罗琨汤艺
Owner HUAWEI TECH CO LTD
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