Method and device of read-write buffer storage location based on field programable logical array

Abstract

This invention discloses a method and a device for reading-writing buffer-storage units based on FPGA, which sets an outer buffer-storage unit to divide it into several small buffer-storage blocks and writes all the description information of a message and its data to said unit to let one message correspond to several blocks, in which, when the FPGA reads information, it reads the buffer-storage block of the located description information first then reads the block where the message data locate according to the obtained message description information. Since it's not necessary to use the internal buffer-storage unit of the FPGA to store message description information and data, it gets rid of the limit of the internal buffer-storage resource of the FPGA and saves the internal buffer-storage.

Description

technical field [0001] The present invention relates to the technical field of Field Programmable Logic Array (FPGA, Field Programmable Gate Array), in particular to a method and device for reading and writing a cache unit based on FPGA. Background technique [0002] When the FPGA processes packets, it usually temporarily stores the packets that exceed the system's processing capability in a certain period of time in the cache, which can improve the system's ability to handle burst traffic. [0003] The FPGA processes grouped messages in units of packets, so it is necessary to distinguish the data of each message when writing and reading cached data. figure 1 It is a schematic diagram of the existing FPGA processing flow. The FPGA puts a large number of data messages received from the upstream chip into the cache first, and then reads a data message from the cache, and after processing and sending it to the downstream chip, reads the next message. figure 1 The cache in the...

AI Technical Summary

Problems solved by technology

[0011] Existing implementation method 1 has the following defects: the cache unit inside the FPGA device is generally very small and can only store dozens of messages. Capability is also very limited, not suitable for applications in high-speed communication systems

[0020] The second existing implementation method has the following defects: since each packet message is divided into description information and data, which are stored in the cache in the FPGA and in the external cache unit respectively, it is limited by the cache size of the FPGA itself. , the FPGA's internal cache can only store the description information of N messages, so the external DDRRAM can only be divided into N blocks to ensure that each block corresponds to the data of a message

But in fact, the storage of each message data does not need such a large block space, so that a lot of space in DDRRAM is wasted in vain

At the same time, using this method also occupies a lot of FPGA internal cache resources.

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