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Amplitude adjusting system for full-duplex multi-level pulse wave and blind activation receiver

A receiver, multi-level technology, applied in the direction of AM carrier system, etc., can solve the problem of complex implementation

Inactive Publication Date: 2006-12-13
RDC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But the implementation of this combination of DFE and Viterbi decoder is still complicated

Method used

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  • Amplitude adjusting system for full-duplex multi-level pulse wave and blind activation receiver
  • Amplitude adjusting system for full-duplex multi-level pulse wave and blind activation receiver
  • Amplitude adjusting system for full-duplex multi-level pulse wave and blind activation receiver

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Embodiment

[0024] like figure 1As shown, the receiver structure 1 of the present invention includes a mixer 10, an analog-to-digital converter (ADC) 11, a fractionally spaced echo canceller 12, a digital resampler 13, a local / remote clock generator 14, a timing recovery PLL A circuit 15 , a blind equalization (BEQ) branch 16 , a linear equalization (LEQ) branch 17 and a 2-to-1 multiplexer (Mux) 18 and a derivative inversion estimator 19 .

[0025] The BEQ branch 16 includes a decision feedback equalizer 161 and a soft level slicer 162 , wherein the LEQ branch 17 includes a linear equalizer 171 , an error feedback equalizer 172 , a hard level slicer 173 and an error level hard limiter 174 . See below for descriptions of these two branches.

[0026] The sampling rate of ADC 11 is flexibly set as (N s +1) / N s multiplied by the transfer rate, where N s is an integer equal to or greater than 1. Therefore, when choosing N s When it is 1, the sampling rate is equal to 2 times the transmis...

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Abstract

The invention discloses a new receiver in the full-duplex multi-quasi PAM system, which is characterized by the following: the receiver utilizes analog digital converter (ADC) with elastic setting (Ns+1) / Ns sampling velocity (Ns equals or is more than 1, which is integral) the fraction gap echo eliminator outputs echo wave in the ADC, which makes time sequence recovery function construct in the digital realm to avoid use complex analog phase non-selective circuit; the receiver adopts decision feedback equalizer with single main valve and flexible grade cutter to reach exciting rapidly, which uses derivative channel estimate optimum locating timing sequence phase to lessen error.

Description

technical field [0001] The present invention relates to equipment and methods for full-duplex multi-level pulse amplitude modulation (PAM) systems, in particular to solutions for full-duplex full-duplex Gigabit Ethernet (Gigabit Ethernet) transceivers. Apparatus and method for a multi-level PAM system. Background technique [0002] Various receiver structures for full-duplex multi-level Pulse Amplitude Modulation (full-duplex multi-level Pulse Amplitude Modulation) have been proposed for implementation in Gigabit (later referred to as Ultra High Speed) Ethernet transceivers In eg US Pat. Nos. 6,771,752 and 6,731,692 and publication by Agere Systems in 2003 titled "IntelliRate Architecture". These structures utilize exactly equal transmission rate (f b ) or twice the transfer rate (2f b ) sampling rate. Using transmission rate sampling requires sampling the received signal at the optimal timing phase position of the analog-to-digital converter (ADC) output, thus requiring...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L27/06
Inventor 曾庆义严明洲柯瑞泰蔡昆颖
Owner RDC SEMICON CO LTD
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