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Welding pad structure for electronic device

A technology for soldering pads and integrated circuits, which is applied to circuits, electrical components, and electrical solid-state devices, etc., can solve the problems of large parasitic capacitance, reduced integrated circuit performance, and close distance between the multi-layer soldering pad structure and the substrate.

Active Publication Date: 2007-01-03
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the distance between the multilayer pad structure and the substrate is shorter than that of a single pad
Therefore, the parasitic capacitance generated between the pad and the substrate is large, which reduces the performance of high-speed and high-frequency integrated circuits

Method used

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  • Welding pad structure for electronic device
  • Welding pad structure for electronic device
  • Welding pad structure for electronic device

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0020] The following fit Figure 3A and 3B Describe the soldering pad structure of the electronic device of the embodiment of the present invention, wherein Figure 3A A schematic plan view of the solder pad structure is drawn, while Figure 3B draw the edge Figure 3A Schematic cross-sectional view of line 3B-3B.

[0021] exist Figure 3B Among them, the pad structure includes: an insulating layer 102 , a top metal layer 108 , a metal layer 106 and a metal layer 104 . The insulating layer 102 is disposed on a substrate 100 . Here, the substrate 100 may be a silicon substrate or other semiconductor substrates. Various elements, such as transistors, resistors, and other well-known semiconductor elements, may be included in the substrate 100 . Furthermore, the substrate 100 may also include an inter-layer dielectric (ILD) layer or an inter-metal dielectric (IMD) layer. In order to simplify the drawing, only a flat substrate is shown here.

[0022] In an embodiment of th...

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PUM

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Abstract

The present invention discloses welded gasket structure of electronic installation for upper and lower layer metal level area ratio in multilayer welded gasket to reduce spurious capacitance and keep welded gasket constructional sturdiness. Said welded gasket structure includes one insulating layer, one top metal level and one metal layer; wherein said insulating layer set on substrate, top metal layer set on insulating layer, metal layer set on insulating layer below top metal layer and electrically connected with top metal layer by at least one insulating layer penetrated conduction plug adapter, metal layer exterior being same with metal layer and having smaller size than it.

Description

technical field [0001] The present invention relates to the manufacture of an integrated circuit, and in particular to a bonding pad design to reduce parasitic capacitance. Background technique [0002] With the improvement of semiconductor technology, the size of devices is continuously reduced to increase the integration level of integrated circuits. The tiny technical problems of the early days are now being highlighted as the size of the devices shrinks. For example, connections such as bonding pads and wires deeply affect device reliability. [0003] figure 1 An existing solder pad is depicted. A metal pad 14 is formed on an insulating layer 12 and is electrically connected to a device (not shown) in or on the underlying substrate 10 through a conductive plug (not shown) in the insulating layer 12 . The insulating layer 12 is usually made of a low dielectric constant material to reduce the RC delay effect caused by the insulating layer 12 and the metal layers and in...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/482H01L23/50H01L23/522
CPCH01L2224/04042H01L2224/05556H01L2224/05554H01L2224/48463H01L24/05H01L2224/05093H01L2924/14
Inventor 林筱筑李胜源
Owner VIA TECH INC