Clock synthesizer with hitless reference switching and frequency stabilization

Abstract

A clock synthesizer for synthesizing an output clock locked to a selected reference clock input has a pair of phase locked loops locked to respective reference clock inputs first generating first and second frequencies. One of the frequencies is selected to control a controlled oscillator for generating an output clock. The frequency offset between the first and second frequencies at the time of switching is stored and added to the frequency controlling the controlled oscillator.

Description

FIELD OF THE INVENTION[0001]This invention relates to the field of precision timing, and in particular to a method of synthesizing an output clock from a selected one of a plurality of reference clocks with hitless switching between the reference clocks and frequency stabilization, and a clock synthesizer implementing the method.BACKGROUND OF THE INVENTION[0002]Precision clock synthesis is important in a number of fields. For this purpose, an output clock may be synthesized from a reference clock input tied to some standard reference using a digital phase locked loop (DPLL). In normal operation, the DPLL will synchronize its output clock to the reference clock.[0003]In order to allow for failure or drift of the reference clock, a plurality (two or more) reference clocks are provided. The DPLL is locked to a selected one of them. In the event that the selected reference clock fails or drifts too far, the input of the DPLL is switched to an alternative reference clock.[0004]It is impo...

AI Technical Summary

Benefits of technology

This patent is about a new clock synthesizer that can lock to two reference clocks even if there is a frequency offset between them. The output clock is stable with neither a frequency hit or a phase error. It uses a controlled oscillator and a frequency tracker to automatically adjust for the frequency offset and ensure no reference switches cause any problems in the output clock. The prototype works in the digital domain, but it also can be used in crystal applications. The method allows for hitless reference switching for both frequency and phase. The stored frequency offset is gradually attenuated to zero over time while the synthesizer remains locked to a particular reference input.

Problems solved by technology

This frequency drift is unacceptable in applications such as that described in U.S. Pat. No. 9,444,470, where a highly stable clock source whose frequency does not change over time is required.

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