Electrically alterable non-volatile memory with n-bits per cell

a non-volatile memory, electric altering technology, applied in static storage, digital storage, instruments, etc., can solve the problems of unstable reference voltage level, complex sensing scheme of multi-level memory devices, and requiring 2.sup.n-1 voltage references

a non-volatile memory, electric altering technology, applied in static storage, digital storage, instruments, etc., can solve the problems of unstable reference voltage level, complex sensing scheme of multi-level memory devices, and requiring 2.sup.n-1 voltage references

US20010019500A1Inactive Publication Date: 2001-09-06BTG INT LTD
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  • Electrically alterable non-volatile memory with n-bits per cell
  • Electrically alterable non-volatile memory with n-bits per cell
  • Electrically alterable non-volatile memory with n-bits per cell

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Embodiment Construction

[0065] A multi-level (or multi-bit) memory device which contains more than one bit of information per memory cell needs accurate and stable reference voltages. The reference voltages allow a multi-level memory cell to be correctly read over various process, voltage, and temperature ranges. The reference voltages must be implemented into the integrated circuit which can accurately sense the multi-level voltage levels of the memory cells as well as track each memory array voltage level as it drifts with the process, voltage, and temperature variations. An unstable or inaccurate reference voltage tends to cause problems such as an improper voltage level read of a bit line, and the like from a memory cell.

[0066] In a 2-bit per memory cell embodiment, the memory cell includes four voltage levels V0, V1, V2, and V3 at each of the bit lines as illustrated by FIG. 15. To uniquely detect each of the four voltage levels, it is necessary to generate at least three reference voltages, each of t...

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Abstract

A multi-bit memory device with a memory cell means for storing input information for an indefinite period of time. The multi-bit memory means stores information in up to Kn memory states (Kn>1). A memory cell programming means and comparator means is also included. The present multi-bit memory device also includes a voltage divider arrangement with pull-up devices in a memory array to provide stable and accurate reference voltages over process, temperature, and voltage variations.

Description

[0001] This application is a continuation-in-part of U.S. patent application Ser. No. 08 / 071,816, filed Jun. 4, 1993 entitled "Electrically Alterable Non-Volatile Memory with N-Bits Per Memory Cell," which is a continuation of U.S. patent application Ser. No. 07 / 652,878, filed Feb. 8, 1991 (now U.S. Pat. No. 5,218,569) entitled "Electrically Alterable Non-Volatile Memory with N-Bits Per Cell."[0002] 1. Field of the Invention[0003] This invention relates to non-volatile memory (NVM) devices; and, more particularly, is concerned with an apparatus and method for providing a multi-level NVM device with stable reference voltages.[0004] 2. Description of the Background Art[0005] In conventional single-bit per cell memory devices, the memory cell assumes one of two information storage states, either an "on" state or an "off" state. This combination of either "on" or "off" defines one bit of information. As a result, a memory device which can store n-bits of data requires n separate memory ...

Claims

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Application Information

Patent Timeline
06 Sep 2001
Publication
US20010019500A1
IPC
G11C11/56
CPC
G11C7/1006; G11C11/5621; G11C11/5628; G11C11/5642; G11C16/12; G11C16/16; G11C16/32; G11C16/3454
Inventors
BANKS, GERALD J.