Circuit, apparatus and method for generating address

Abstract

A circuit and a method for generating an address, which can generate a plurality of types of address on the basis of a reference address, and an apparatus for generating an address, which can generate the different addresses from one another by using a plurality of circuits described above at a plurality of steps. The circuit (200) for generating an address, comprises: a multiplex counter (30) comprising a counter (31) for counting a pulse number of a clock signal to generate a count number represented by binary bit and a bit shift circuit (33) for shifting the count number, to generate an output count number; and an arithmetic circuit (20) for operating an address signal on the basis of the output count number and a reference address signal, to output the address signal to a semiconductor memory as an object of test.

Description

[0001] 1. Field of the Invention[0002] The present invention relates to a circuit, an apparatus and a method for generating an address in a semiconductor memory testing device.[0003] 2. Description of Related Art[0004] The circuit for generating an address is one in a semiconductor memory testing device, for generating an address signal of a memory cell to be read (read out) or to be written (written in) at a high speed, on the basis of the predetermined algorithm.[0005] FIG. 6 is a view showing an example of a circuit 100 for generating an address according to an earlier development. In FIG. 6, the circuit 100 for generating an address comprises a counter 10 and ALU (Arithmetic and Logic Unit) 20.[0006] The counter 10 counts the pulse number of a clock pulse signal by +1, which gives a pulse as a clock and which is inputted from the outside of the circuit 100. Thereafter, the counter 10 outputs the count number to ALU 20.[0007] When the count number is inputted from the counter 10 ...

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