Random access memory device and method for driving a plate line segment therein

Abstract

A random access memory device includes a number of memory cells, with word lines, plate lines, and bit lines coupled to the memory cells. A switch, controlled by a word line, couples one end of the plate line to a first global plate line, while another switch, controlled by a second global plate line, couples the one end of the plate line to a reference voltage. The plate lines are charged by the first global plate line, which improves operational speed of the device and reduces loading of the word lines.

Description

[0001] 1. Field of the Invention[0002] The present invention relates generally to a random access memory device and, more particularly, to a nonvolatile ferroelectric random access memory device with a segmented plate line and a method for driving a plate line segment.[0003] 2. Description of Related Art[0004] Random access memory devices are well known in the art. One type of random access memory is a ferroelectric random access memory (FRAM), which employs a ferroelectric capacitor as the storage element for each memory cell. A FRAM stores a logic state based on the electrical polarization of the corresponding ferroelectric capacitor. When a sufficient voltage potential difference (i.e., above the switching threshold or coercive voltage level) is applied to the plates of the ferroelectric capacitor, the ferroelectric material of the capacitor is polarized in the direction of the electric field.[0005] Typically, one plate of a ferroelectric capacitor is coupled to a bit line via an...

AI Technical Summary

Benefits of technology

The present invention provides a random access memory device with reduced loading on the word lines and plate lines, which increases the voltage level ramp-up times on the word lines and plate lines without area penalty. The reduced loading of the word lines and plate lines enables increased operational speed of the device, reduces loading of the word lines and plate lines, and improves access time and cycle time of the memory cells. The invention also provides a method of operating the device by charging the plate lines through a local plate line decoder or other circuit, instead of directly by the row decoder, which further reduces the area penalty and improves operational speed, access time, and cycle time of the memory cells.

Problems solved by technology

A drawback of this scheme is that a segmented plate line pull-down circuit (one of which is circled in FIG. 1 and labeled PLPD) is required, which increases the loading of the word line and the overall size of the circuitry (i.e., chip area).

One drawback of this scheme is that the extent of the loading of the word line and the plate lines can limit the voltage level ramp-up, which in turn can limit device operation speed.

Thus, the operational speed can be limited.

Moreover, pull-down circuits are not connected, so the area penalty is small.

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