System for improving thermal stability of copper damascene structure

Abstract

Disclosed is a system for fabricating a semiconductor device (100). An interconnect structure (110) is formed on the semiconductor device (100) and a cap (112) is deposited over the interconnect structure (110). The interconnect structure (110) is annealed with the overlying cap (112) in place. The cap (112) is then removed after the interconnect structure (110) is annealed.

Description

FIELD OF THE INVENTION [0001] The invention is related generally to the field of fabricating interconnect structures for integrated circuits and, more specifically, to improving the thermal stability of copper damascene interconnect structures. BACKGROUND OF THE INVENTION [0002] This application claims priority from Provisional Application Ser. No. 60 / 344,465, filed on Dec. 28, 2001. [0003] Since the invention of integrated circuits, the number of devices on a chip has grown at a near-exponential rate. The fabrication methods of the semiconductor industry have been modified and improved continuously for almost four decades. With each improved method, the capacity of a single semiconductor chip has increased from several thousand devices to hundreds of million devices. Future improvements will require integrated circuit devices such as transistors, capacitors, and connections between devices to become even smaller and more densely populated on the chip. [0004] The increased packing d...

AI Technical Summary

Benefits of technology

[0009] As should now be apparent, a method of forming copper interconnect structures that does not add excessive costs or procedures to the fabrication process is now needed, providing for fabrication of more reliable semiconductor devices while overcoming the aforementioned limitations of conventional methods.

Problems solved by technology

The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process.

Unfortunately, copper is very difficult to etch in a semiconductor process flow.

During anneal steps, deposited copper interconnects frequently form voids at via bottoms and other interfaces, which may ultimately cause device failure.

A low temperature anneal, however, will not completely stabilize the deposited copper and also result in device failure.

Stresses within the copper interconnect structure may cause the interconnect to fail during the high temperature annealing process, which also causes via open failures.

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