52results about How to "Reliably fabricated" patented technology

In order to fabricate a high performance thin film semiconductor device using a low temperature process in which it is possible to use low price glass substrates, a thin film semiconductor device has been fabricated by forming a silicon film at less than 450 DEG C., and, after crystallization, keeping the maximum processing temperature at or below 350 DEG C. In applying the present invention to the fabrication of an active matrix liquid crystal display, it is possible to both easily and reliably fabricate a large, high-quality liquid crystal display. Additionally, in applying the present invention to the fabrication of other electronic circuits as well, it is possible to both easily and reliably fabricate high-quality electronic circuits.

A multi-layer thin film for encapsulation and the method thereof are provided. The multi-layer thin film for encapsulation includes a protective layer composed of aluminum oxide, a single or double barrier layer composed of silicon nitride (SiNx), and a mechanical protective layer composed of silicon dioxide (SiO2). The multi-layer thin film can be economically fabricated by using the existing equipment, and has a high level of light transmission over 85% while showing a low level of oxygen and moisture penetration. Additionally, due to superior adhesive strength between the thin films, and high resistance against impacts by heat or ion during a fabricating process, reliability of fabrication is enhanced, and it can thus efficiently used in encapsulating an organic light-emitting device (OLED), a flexible organic light emitting device (FOLED) in a display field, and the cells such as a thin film battery and a solar cell.

A ferrule assembly having highly protruding optical fibers and a corresponding method of efficiently, precisely and repeatedly fabricating the ferrule assemblies are provided. In this regard, a ferrule assembly is provided that includes a plurality of optical fibers extending at least about 3.5 μm beyond the front face. The end portions of the optical fibers of the ferrule assembly may also be substantially coplanar with the end portions of the optical fibers differing in position from one another by no more than 100 nm. The ferrule assembly may be efficiently fabricated by polishing the optical fibers to a desired protrusion without first grinding or polishing the optical fibers to be flush with the front face of the ferrule. The ferrule assembly may be even more efficiently fabricated in instances in which the ferrule includes at least one polishing feature, such as an outwardly extending pedestal or a recessed portion.

A method of fabricating a thin film pattern improve the life of a blanket and reduce the cost and improve reliability in forming the thin film pattern. The method includes injecting an etch resist solution into a blanket on a printing roller, wherein the etch resist solution includes a printing solvent that satisfies the condition 6>δsolvent or δsolvent>11, where δsolvent is the solubility parameter of the solvent, or satisfies the condition 6<δsolvent<11 and μ<2(D), where μ is the dipole moment of the solvent; rotating the printing roller to uniformly coat the etch resist solution on the blanket; rolling the printing roller coated with the etch resist solution onto a printing plate to pattern the etch resist solution to thereby form an etch resist pattern; transferring the etch resist pattern from the printing roller to a substrate; hardening the etch resist pattern; and forming a desired thin film pattern on the substrate using the etch resist pattern.

This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.

In order to fabricate a contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, on a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on the semiconductor surface, an insulator layer is formed on the semiconductor surface and a sacrificial layer is subsequently formed on the insulator layer, then material plugs are produced on the sacrificial layer for the purpose of defining contact openings between the mutually adjacent gate electrode tracks, the sacrificial layer is etched to form material plugs with the underlying sacrificial layer blocks, after the production of the vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, an essentially planar surface being formed, then the sacrificial layer material is etched out from the vitreous layer and the uncovered insulator material is removed above the contact openings on the semiconductor surface and, finally, the contact opening regions are filled with a conductive material.

Disclosed is a method of fabricating a flexible device, which includes surface-treating one or both sides of a carrier plate so that regions with different surface-treatments are formed on the same side of the carrier plate, forming a glass-filler reinforced plastic substrate film on the surface-treated carrier plate, forming thin film patterns on the glass-filler reinforced plastic substrate film, and separating the glass-filler reinforced plastic substrate film having the thin film patterns formed thereon from the carrier plate, and in which the surface-treating of the carrier plate enables the glass-filler reinforced plastic substrate film to be easily separated from the carrier plate without an additional process such as using a solvent or a laser release technique.

A method for fabricating an electrical connection structure of a circuit board is proposed. The circuit board is provided with a plurality of pads on a surface thereof and with a plurality of conductive structures therein for electrically connecting the pad. A plurality of openings is formed penetrating through an insulating layer provided on the circuit board to expose the pad. Subsequently, a conductive base is attached to one surface of the circuit board for electrically connecting the pad. By such arrangement, a conductive material can be formed on the pad located on the other surface of the circuit board by an electroplating process via the conductive base, the pad on the surface, and the conductive structure within the circuit board.

Magnetic motor component sleeves (209) for motor components with the sleeves (209) having various helpful magnetic characteristics, such as high magnetic permeability; magnetic saturation; residual (or remanent) magnetization; anisotropic magnetic properties. Method for making a magnetic linear motor shaft (202), including thermal treatment to temporarily change the dimensions of various shaft components to allow tight assembly.

A method for fabricating conductive bumps of a circuit board is proposed. First of all, a circuit board having a first surface and a corresponding second surface is provided. A circuit structure having a plurality of conductive pads is formed on each of the first surface and the second surface, and conductive structures are formed in the circuit board for electrically connecting the circuit structures. Also, an insulating layer having a plurality of openings penetrating therethrough is formed on the circuit board for exposing the conductive pad. Then, a conductive layer is formed on a surface of the insulating layer having the opening formed on the first surface of the circuit board. An electroplating process is performed via the conductive layer and the conductive structure, such that a conductive bump is formed on the conductive pad located on the second surface of the circuit board. Subsequently, a resist layer is formed on the second surface of the circuit board to cover the conductive bump, and another resist layer having openings penetrating therethrough is formed on the first surface of the circuit board to expose the conductive pad. Finally, a conductive bump is formed on the conductive pad located on the first surface of the circuit board by an electroplating process. By such arrangement, the conductive bumps are successively formed on the first surface and the second surface of the circuit board.

A magnetic head including a dual layer induction coil. Following the deposition of a first magnetic pole (P1) a first induction coil is fabricated. Following a chemical mechanical polishing (CMP) step a layer of etchable insulation material is deposited followed by the fabrication of a second induction coil etching mask. A reactive ion etch process is then conducted to etch the second induction coil trenches into the second etchable insulation material layer. The etching depth is controlled by the width of the trenches in an aspect ratio dependent etching process step. The second induction coil is next fabricated into the second induction coil trenches, preferably utilizing electrodeposition techniques. Thereafter, an insulation layer is deposited upon the second induction coil, followed by the fabrication of a second magnetic pole (P2) upon the insulation layer.

A window bird house is advantageously configured for easy transport and storage, and is a low cost alternative to prior art bird houses. The window bird house includes a housing having a plurality of walls and a floor which are collapsible upon each other for compact transport and storage. One of the walls includes a viewing opening for observing birds in the housing. Additionally, the rear wall may be removably secured to a first side of a window so that inside of the housing is visible from a second side of the window. Also, one of the walls includes an opening for ingress and egress of birds. A cover may be attached to the second side of the window for selecting covering the viewing opening thereby mitigating disruptions to the birds. The window bird house may be fabricated from die cut corrugated plastic sheet.

The invention provides a structuring method, in particular for stepped wafer or die surfaces. The method includes photolithographically exposing a pattern comprising at least a first pattern portion and a second pattern portion onto a surface, said surface comprising at least a first surface portion at which a tangential plane to the surface extends in a first plane and a second surface portion at which a tangential plane to the surface extends in a second plane not coinciding with the first plane. The method comprises a first exposure step, in which the first pattern portion is exposed. Therein, the first pattern portion is focused into a first focal plane. The method further comprises a second exposure step, in which the second pattern portion is exposed. Therein, the second pattern portion is focused into a second focal plane which is different from the first focal plane.

A method of forming a hardened skin on one or more surfaces of a molded article. In an exemplary method, a formable material is mixed with a blowing agent to form a foam material. The foam material is placed in a flow molding apparatus such that a first surface of the foam material is in contact with a first mold section and a second surface of the foam material is in contact with a second mold section. In operation, an alternating dielectric field is applied across the foam material to form the molded article. At the end of the molding cycle, the first and / or second surfaces of the foam material remain under the decomposition temperature of the blowing agent and are not blown so as to form one or more thicknesses of hardened skin on the molded article.

A carrying structure of electronic components is proposed. The carrying structure includes at least one supporting board with at least one cavity disposed thereon, at least one adhesive layer formed on the supporting board, and at least one electronic component having an active face and a non-active face located in the cavity. The gap between the cavity and the electronic component is filled with a portion of the adhesive layer, and thus the electronic component is fixed in the cavity of the supporting board.

An in-mold decoration fabrication of injection molding is provided as follows. First, a plastic substrate is provided and a mask is disposed on the plastic substrate. A patterned metal film is formed on a surface of the plastic substrate without covering the mask. After the mask is removed, an ink pattern is formed selectively on the patterned metal film. Then, a plurality of forming units on the plastic substrate are preformed and separated to each other by trimming the plastic substrate. Finally, a step of resin injection is provided to cover the patterned metal film, ink pattern of each of the forming units and the exposed surface thereof.

Provided are a semiconductor technique, and more particularly, to a variable resistor, a non-volatile memory device using the same, and a method of fabricating the same. The variable resistor may include a first electrode including titanium (Ti); a second electrode for forming a Schottky barrier; and a stacked structure including an oxygen-deficient hafnium oxide film (HfO2-x, 0<x<2) between the first electrode and the second electrode, an oxygen-deficient titanium oxide (TiOx) film between the oxygen-deficient hafnium oxide film and the first electrode, and a stoichiometric tantalum oxide (Ta2O5) film between the oxygen-deficient hafnium oxide film and the second electrode.

Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.

A method for fabricating conductive bumps of a circuit board is proposed. First of all, a circuit board having a first surface and a corresponding second surface is provided. A circuit structure having a plurality of conductive pads is formed on each of the first surface and the second surface, and conductive structures are formed in the circuit board for electrically connecting the circuit structures. Also, an insulating layer having a plurality of openings penetrating therethrough is formed on the circuit board for exposing the conductive pad. Then, a conductive layer is formed on a surface of the insulating layer having the opening formed on the first surface of the circuit board. An electroplating process is performed via the conductive layer and the conductive structure, such that a conductive bump is formed on the conductive pad located on the second surface of the circuit board. Subsequently, a resist layer is formed on the second surface of the circuit board to cover the conductive bump, and another resist layer having openings penetrating therethrough is formed on the first surface of the circuit board to expose the conductive pad. Finally, a conductive bump is formed on the conductive pad located on the first surface of the circuit board by an electroplating process. By such arrangement, the conductive bumps are successively formed on the first surface and the second surface of the circuit board.

Microelectronic packages include a first microelectronic substrate having a first face and a first AC-coupled interconnect element on the first face. A second microelectronic substrate includes a second face and a second AC-coupled interconnect element on the second face. A buried solder bump extends between the first and second faces, and is at least partially buried beneath the first and / or second faces, to maintain the first and second AC-coupled interconnect elements in closely spaced apart relation. The buried solder bump also may couple DC power between the first and second substrates. Other technologies also may be used to maintain the AC-coupled interconnect elements in closely spaced apart relation and to couple DC power between the substrates. The first and second AC-coupled interconnect elements may be first and second capacitor plates, first and second inductors and / or first and second combined inductive and capacitive elements.