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Semiconductor wafer and manufacturing process thereof

a technology of semiconductor and manufacturing process, applied in the field of semiconductor, can solve the problems of high increase in the manufacturing cost of the die, high cost of laser cutting, and inability to standardize the quality of each of the dies, and achieve the effect of extending the use area of the di

Inactive Publication Date: 2005-12-22
ADVANCED ANALOG TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0011] A main object of the present invention is to provide a semiconductor wafer, wherein the terminal pad are disposed along a scribe line of a semiconductor wafer to electrically connect with the die, so as to enlarge the usage area of the die.
[0013] Another object of the present invention is to provide a semiconductor wafer, wherein the terminal pad is formed as a comb shape to minimize the residue is stayed at the cutting tip of the cutting tool when a cutting tool cuts off the die along the scribe line, so as to enhance the cutting operation of the die.
[0014] Another object of the present invention is to provide a semiconductor wafer, wherein since the terminal pad is moved from the die to the scribe line of the wafer body, the usage area of the die is enlarged such that more integrated circuits can be added into the die for enhancing the function of the die.
[0015] Another object of the present invention is to provide a semiconductor wafer, wherein no substantial structural design of the die is altered such that the semiconductor wafer can be tested by any existing trimming test, so as to minimize the manufacturing cost of the present invention.
[0016] Another object of the present invention is to provide a trim fuse semiconductor wafer, wherein the manufacturing process thereof is as simple as repositioning the terminal pad from the die to dispose along the scribe line of the wafer and electrically connecting the terminal pad with the die via the conductive arrangement. Therefore, no extra component is required in the present invention so as to further lower the manufacturing cost of the present invention.

Problems solved by technology

However, the operation of the laser cut is costly and complicated so as to highly increase the manufacturing cost of the die.
In addition, during the operation of the laser cut, the voltage of each of the dies cannot be predicted so that the quality of each of the dies cannot be standardized.
Furthermore, the conventional semiconductor wafer has several drawbacks.
Therefore, the limited size of each of the dies can only hold up to a certain number of pads thereon.
In other words, the complicated integrated circuits are limited on the size of each of the dies so as to highly increase the manufacturing cost of the semiconductor wafer.
The terminal pads are useless after the measurement.

Method used

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  • Semiconductor wafer and manufacturing process thereof
  • Semiconductor wafer and manufacturing process thereof
  • Semiconductor wafer and manufacturing process thereof

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Embodiment Construction

[0025] Referring to FIGS. 1 and 2 of the drawings, a semiconductor wafer according to a preferred embodiment of the present invention is illustrated, wherein the semiconductor wafer comprises a wafer body 10, and a plurality of analog IC dies 20 spacedly and alignedly formed on the wafer body 10 to define a scribe line 11 as a margin formed between each two dies 20, wherein each of the dies 20 has an internal circuit 21 formed therewithin and at least a terminal pad 22 formed along the scribe line 11.

[0026] The semiconductor wafer further comprises a conductive arrangement 30 which comprises at least a conductive element 31 formed on the wafer body 10 to electrically connect the terminal pad 22 with the internal circuit 21 of the die 20 in such a manner that when the die 20 is cut off from the wafer body 10 along the scribe line 11, the terminal pad 22 is cut off from the die 20 so as to keep the internal circuit 21 in the die 20.

[0027] The present invention further provides a pro...

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Abstract

A semiconductor wafer includes a wafer body, a plurality of analog IC dies spacedly and alignedly formed on the wafer body to define a scribe line as a margin formed between each two dies wherein each of the dies has an internal circuit formed therewithin and at least a terminal pad formed along the scribe line, and a conductive arrangement including at least a conductive element formed on the wafer body to electrically connect the terminal pad with the internal circuit of the die in such a manner that when the die is cut off from the wafer body along the scribe line, the terminal pad is cut off from the die so as to keep the internal circuit in the die.

Description

CROSS REFERENCE OF RELATED APPLICATION [0001] This is a divisional application of a non-provisional application, application Ser. No. 10 / 841,035 filed on May 6, 2004.BACKGROUND OF THE PRESENT INVENTION [0002] 1. Field of Invention [0003] The present invention relates to semiconductor, and more particularly to a semiconductor wafer and its manufacturing process thereof, wherein the terminal pad is disposed along a scribe line of a semiconductor wafer to enlarge the usage area of the analog IC die. [0004] 2. Description of Related Arts [0005] A conventional semiconductor wafer comprises a wafer body and a plurality of dies spacedly formed on the wafer body to define a scribe line as a margin between each two dies. Accordingly, each of the dies, which is also called as an analog IC chip, is an integrated circuit consisting of silicon based substrate. [0006] Before each of the dies is cut into an individual component, a wafer test must be performed to ensure each of the dies is function...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/301H01L21/44H01L23/544
CPCH01L22/32
Inventor CHEN, WEI-JUNGCHANG, YUNG-CHINGHUANG, JAW-SHINFANG, CHENG-YUYU, CHIEN-PENG
Owner ADVANCED ANALOG TECH INC