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Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system

a memory system and multi-counter technology, applied in the field of multi-counter first-in, first-out memory, can solve problems such as undesirable user processing of data

Active Publication Date: 2006-01-26
INTEGRATED DEVICE TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0023] Because each read operation to the present queue and new queue is accurately counted by the first read counter and the second read counter, the present queue read count pointer and new queue read count pointer are accurate, without requiring a pipeline scheme or a forced-word-fall-through (FWFT) restriction on the data output during a queue switch.

Problems solved by technology

However, this scheme undesirably requires the user to process data during cycle QS2.

Method used

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  • Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system
  • Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system
  • Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system

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Embodiment Construction

[0031] The present invention includes a multi-queue flow-control device, which is implemented on a single chip. The multi-queue device can be configured to implement between 1 and 128 discrete FIFO queues. The user has full flexibility configuring queues within the device, being able to program the total number of queues between 1 and 128. The user can also independently select the individual queue depths.

[0032] All queues within the device have a common data input bus (write port), and a common data output bus (read port). Data written to the write port is directed to a respective queue via an internal de-multiplexer, which is addressed by a user. Data read from the read port is accessed from a respective queue via an internal multiplexer, addressed by the user. Data writes and reads can be performed at high speeds (up to 200 MHz, with access times of 3.6 ns in accordance with one embodiment of the present invention). Data write and read operations are totally independent of each ...

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PUM

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Abstract

A method of operating a multi-queue device, including: (1) storing a plurality of read (write) count pointers, wherein each of the read (write) count pointers is associated with a corresponding queue of the multi-queue device, (2) providing a read (write) count pointer associated with a present queue to read (write) flag logic, (3) adjusting the read (write) count pointer associated with the present queue in response to each read (write) operation performed by the present queue, (4) indicating a read (write) queue switch from the present queue to a next queue, (5) retrieving a read (write) count pointer associated with the next queue; and then (6) simultaneously providing the read (write) count pointer associated with the present queue and the read (write) count pointer associated with the next queue to the read (write) flag logic.

Description

RELATED APPLICATIONS [0001] The present application is related to, and incorporates by reference, U.S. Provisional Patent Application Ser. No. 60 / 591,499 filed by Mario Au, Jason Z. Mo, Xiaoping Fang, Hui Su, Cheng-Han Wu, Ta-Chung Ma and Lan Lin on Jul. 26, 2004. The present application is also related to, and incorporates by reference, U.S. Provisional Patent Application Ser. No. 60 / 600,347 filed by Mario Au, Jason Z. Mo, Xiaoping Fang, Hui Su, Cheng-Han Wu, Ta-Chung Ma and Lan Lin on Aug. 9, 2004. [0002] The present application is also related to, and incorporates by reference, the following commonly owned, co-filed U.S. patent applications. [0003] U.S. patent application Ser. No. ______ [Attorney Docket No. IDT-1892]“Interleaving Memory Blocks to Relieve Timing Bottleneck in a Multi-Queue First-In First-Out Memory System” by Mario Au, Jason Z. Mo, Ta-Chung Ma and Lan Lin. [0004] U.S. patent application Ser. No. ______ [Attorney Docket No. IDT-1893]“Mark / Re-Read and Mark / Re-Write...

Claims

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Application Information

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IPC IPC(8): G11C8/00
CPCG06F5/065G11C8/16G06F5/14
Inventor AU, MARIOMO, JASON Z.
Owner INTEGRATED DEVICE TECH INC
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