Fast digital carrier frequency error estimation algorithm using synchronization sequence
a digital carrier and error estimation technology, applied in the field of communication systems, can solve the problems of increasing the appearance of a bias error in the carrier frequency error estimation, too expensive computationally for certain applications, and undesirable methods,
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[0024] In accordance with one aspect of the invention, an improved digital frequency estimation algorithm is provided that overcomes the complexity of DFT algorithms and the additional overhead associated with PLL approaches by “back processing” the synchronization section of a received waveform. The algorithm allows for a frequency estimate to be formed from a relatively short segment of input data using overlapping symbols extracted from the data. By correlating over short segments, the signal-to-noise ratio is improved for the estimate. Since a synchronization (SYNC) sequence is known by a demodulator in a receiver, the demodulator can store the received digitized inphase (I) and quadrature (Q) baseband signals during the SYNC section of the waveform. Once SYNC is detected, the stored I and Q signals received during the SYNC section are read out of memory and processed to determine the carrier frequency error. The carrier frequency error can be determined entirely in the time-dom...
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