Device with scavenging spacer layer
a technology of spacer layer and scavenging spacer, which is applied in the direction of semiconductor devices, basic electric elements, electrical apparatus, etc., can solve the problems of unfavorable thin transition layer, and inability to meet the requirements of gate dielectric stack overall electrical thickness
Inactive Publication Date: 2007-06-28
INTEL CORP
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Benefits of technology
The patent describes a method and apparatus for making semiconductor devices with a high-k gate dielectric layer. The invention addresses the issue of gate leakage currents in MOS field-effect transistors with very thin silicon dioxide based gate dielectric layers. The invention proposes using a scavenging spacer layer to reduce the thickness of the gate dielectric stack. The invention also describes a method for forming a device with a scavenging spacer layer, which includes a cross sectional side view of the semiconductor device. The technical effects of the invention include reducing gate leakage currents, improving the electrical thickness of the gate dielectric stack, and improving the overall performance of the semiconductor device.
Problems solved by technology
MOS field-effect transistors with very thin silicon dioxide based gate dielectrics may experience unacceptable gate leakage currents.
The presence of a thick transition layer may unfavorably contribute to the overall electrical thickness of the gate dielectric stack.
Method used
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Embodiment Construction
[0008] In various embodiments, an apparatus and method relating to the formation of a device with a scavenging spacer layer are described. In the following description, various embodiments will be described. However, one skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other replacement and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
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Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen-scavenging spacer layer on side walls of the high-k gate dielectric layer and metal gate may reduce such oxidation during high temperature processes.
Description
BACKGROUND Background of the Invention [0001] MOS field-effect transistors with very thin silicon dioxide based gate dielectrics may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, instead of silicon dioxide, can reduce gate leakage. When conventional processes are used to form such transistors, a silicon dioxide transition layer may form between the high-k dielectric and the substrate. This transition layer may grow larger during high temperature processes when available oxygen may react with the substrate to form more silicon dioxide. The presence of a thick transition layer may unfavorably contribute to the overall electrical thickness of the gate dielectric stack. BRIEF DESCRIPTION OF THE DRAWINGS [0002]FIG. 1 is a cross sectional side view that illustrates the semiconductor device of one embodiment of the present invention. [0003]FIG. 2 is a cross sectional side view that illustrates the electrode in more deta...
Claims
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IPC IPC(8): H01L29/94
CPCH01L29/0847H01L29/513H01L29/517H01L29/6656H01L29/66636
Inventor METZ, MATTHEW V.DOCZY, MARK L.BRASK, JUSTIN K.CHAU, ROBERT S.
Owner INTEL CORP