Semiconductor integrated circuit

Abstract

A semiconductor integrated circuit includes a wiring capable of connecting a plurality of chips on a wafer and has a configuration which is capable of cutting the wiring electrically and which allows all the chips to be tested at one time. Specifically, an exclusive test circuit region capable of being shared for testing the plurality of chips is formed on the wafer, and a test circuit is removed from each chip. Terminals of the chips and a terminal of the test circuit are connected through a wiring on the wafer or a device outside the wafer to enable a general test to be performed in burn-in.

Description

BACKGROUND OF THE INVENTION[0001]The present invention relates to a semiconductor integrated circuit and particularly relates to a test for a wafer-level semiconductor integrated circuit.[0002]Semiconductor integrated circuits are subjected to various tests, such as a probe test in a wafer level, a final test after packaged with the wafer divided, a burn-in test for degrading transistors that are going to be out of order by operating the transistors in adverse environment, a test thereafter, and so on.[0003]In the probe test and the final test, semiconductor integrated circuits packaged or on a wafer are tested one by one with the use of a test circuit included in each of the semiconductor integrated circuits. A recent increase in scale of semiconductor integrated circuits, however, extends a test time to increase the rate of the test cost occupying the product cost.[0004]Further, in the burn-in test, the semiconductor integrated circuits are operated under a condition of high tempe...

AI Technical Summary

Benefits of technology

[0011]The present invention has been made in view of the foregoing and has its object of providing a semiconductor integrated circuit of which test cost is reduced by performing a wafer-level test in burn-in.

Problems solved by technology

A recent increase in scale of semiconductor integrated circuits, however, extends a test time to increase the rate of the test cost occupying the product cost.

The burn-in device has a limited number of signals usable for inputting and outputting a test pattern.

With a smaller number of usable terminals, the test itself cannot prove whether or not all of the semiconductor integrated circuits operate normally.

Further, the test circuit, which is unnecessary in a normal operation, is included in each chip, leading to an undesired increase in chip cost.

This conventional technique, however, invites an increase in an enormous number of wirings for the test to increase the wiring length and the wiring area in the isolation region, and therefore, problems, such as signal delay, reduction in the number of chips that can be formed on a wafer, which is accompanied by an increase in area of the isolation region, and the like are involved to make the technique to be impractical.

Further, the wirings connected to an external terminal in the isolation region are not subjected to processing after chip division, involving problems in quality and the like.

In addition, all chips on the wafer are tested at one time, which requires enormous electric power, inviting problems that a general burn-in device cannot perform the test, and the like.

Though the burn-in requires several hours, transistors repeat ON / OFF operation purposelessly during the time, which means ineffective use of time.

The increase in scale of the semiconductor integrated circuits leads to an increase in test time.

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