Reduced-resistance finfets by sidewall silicidation and methods of manufacturing the same

Abstract

In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source / drain diffusion region of the finFET on the substrate. Each source / drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.

Description

[0001] The present application is a continuation of and claims priority to U.S. patent application Ser. No. 11 / 316,244, filed Dec. 22, 2005, which is hereby incorporated by reference herein in its entirety.FIELD OF THE INVENTION [0002] The present invention relates generally to semiconductor device manufacturing, and more particularly to reduced-resistance finFETs and methods of manufacturing the same. BACKGROUND [0003] A finFET is a transistor that includes a narrow fin (e.g., of silicon) with gate conductors either on two opposing sidewalls of the fin, or on two opposing sidewalls and the top surface of the fin. An overall resistance of the finFET is strongly determined by the area of an interface between a silicide layer and silicon in the source / drain regions of the finFET. Conventional finFETs may include a silicide formed on portions of a top surface of silicon in a source / drain region of the finFETs. However, such finFETs exhibit a high resistance, which is undesirable, becau...

AI Technical Summary

Benefits of technology

The approach results in a reduced resistance for the finFET by increasing the silicide-silicon interface area, improving current drivability and reducing series resistance compared to conventional finFETs.

Problems solved by technology

However, such finFETs exhibit a high resistance, which is undesirable, because of the small area available at the top surface of the fin.

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