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All-digital timing control for multi-channel full-duplex transceiver

a multi-channel, full-duplex technology, applied in the direction of digital transmission, transmission, duplex signal operation, etc., can solve the problems of unknown timing with respect to which the transmitter of the remote transceiver transmits the multi-level signal, and the communication channel usually introduces certain distortions

Active Publication Date: 2009-12-31
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a method for controlling a device that can transmit and receive signals simultaneously. The method involves generating two clocks, one for transmitting and one for receiving. The receiving clock is then used to sample and equalize the received signals. These equalized signals are then converted into a new form using the transmitting clock. The technical effect of this method is that it allows for more efficient and accurate signal processing, resulting in better performance of the device.

Problems solved by technology

First, the communication channel usually introduces certain distortion to the multi-level electrical signal.
Second, the timing with respect to which the transmitter of the remote transceiver transmits the multi-level signal is unknown.
Third, due to simultaneous transmitting and receiving, an interference known as “echo” originated from the transmitter of the local transceiver enters into the receiver of the local transceiver for the same channel.
Fourth, due to using multiple channels, an interference known as “NEXT” (“near-end cross talk”) originated from the transmitter of the local transceiver of one channel enters into the receiver of the local transceiver of another channel.

Method used

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  • All-digital timing control for multi-channel full-duplex transceiver
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  • All-digital timing control for multi-channel full-duplex transceiver

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Embodiment Construction

[0016]The present invention relates to timing control of transceiver, in particular to all-digital timing control for multi-channel full-duplex transceiver. While the specifications described several example embodiments of the invention considered best modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.

[0017]A 4-channel full-duplex PAM transceiver 200 in accordance with the present invention is depicted in FIG. 2A. The four channels are labeled by identifiers A, B, C, and D, respectively. Transceiver 200 comprises: four hybrid circuits 210A˜D (hereafter, the form “210A˜D” refer to 210A, 210B, 210C, and 210D) for interfacing with four media-dependent interfaces MDIA˜D (herea...

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PUM

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Abstract

A multi-channel full-duplex transceiver is disclosed. The transceiver comprises: a clock generator for generating a first clock and a second clock based on a control code; a plurality of transmitters for transmitting a plurality of outgoing signals onto a plurality of channels, respectively; a plurality of receivers for receiving, sampling, and equalizing in parallel a plurality of incoming signals from said plurality of channels, respectively, to generate in parallel a plurality of equalized signals, respectively; a symbol-rate-converters for converting in parallel said equalized signals into a plurality of refined signals, respectively. In a first operation mode, the control code is established by detecting a timing difference between an output clock of the clock generator and a reference clock. In a second operation mode, the control code is established by detecting a timing embedded in one of said refined signals.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority benefits under 35 U.S.C. §119(e) from U.S. Provisional Application No. 61 / 075,693, filed on Jun. 25, 2008, entitled “ALL-DIGITAL TIMING CONTROL FOR MULTI-CHANNEL FULL-DUPLEX TRANSCEIVER” which is hereby incorporated herein in its entirety by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates generally to timing control of transceiver, in particular to all-digital timing control for multi-channel full-duplex transceiver.[0004]2. Description of Related Art[0005]As depicted in FIG. 1, a full-duplex communication system 100 comprises a first transceiver 110, a second transceiver 120, and a communication media 130. The first (second) transceiver 110 (120) comprises a transmitter 112 (124), a receiver 114 (122), and a duplexer 116 (126). The first transceiver 110 receives a first transmitting data TX1, encodes / modulates the data into a first electrical ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H04B3/20H04L5/14
CPCH04L5/1469H04L7/0029H04L2025/03636H04L25/03044H04L25/067H04L7/0079
Inventor LIN, CHIA-LIANG
Owner REALTEK SEMICON CORP