Flexible read- and write-monitored and buffered memory blocks
a memory block and read-write technology, applied in the direction of memory address/allocation/relocation, instruments, error detection/correction, etc., can solve the problems of invalid data cached at the current location, serious problems can occur, and need to invalidate cache entries
Inactive Publication Date: 2010-12-30
MICROSOFT TECH LICENSING LLC
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AI Technical Summary
Benefits of technology
The patent describes a way to monitor access to memory blocks in a computing system with multiple threads. The system includes a processor that can set and test monitors on memory blocks to observe accesses by other agents. The processor can detect conflicts between memory accesses and reset the monitors accordingly. The technical effect of this invention is to improve the performance and reliability of computer systems by optimizing memory accesses and reducing conflicts between threads.
Problems solved by technology
One particular challenge relates to memory access.
As such, there is often a need to invalidate cache entries and replace them with other data from the system memory.
If the data is indicated as invalid, then the data cached at the current location is invalid and is not used.
When operations are performed to exchange money from one account to another, serious problems can occur if the system is allowed to credit one account without debiting another account.
However, in each of the above systems there is no way for software to change or inspect that state.
Method used
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[0015]Some embodiments described herein implement an extension of baseline cache-based hardware transactional memory. Some embodiments, through their included features, may add generality, implementation flexibility / agility, and thereby make possible new non-transactional memory uses of the facility. In particular, some embodiments include the ability to, per hardware thread, for a particular thread, using software and a processor instruction set architecture interface, set and test memory access monitoring indicators to determine if blocks of memory are accessed by other agents. An agent is a component of a computer system that interacts with shared memory. For example it may be a CPU core or processor, a thread in a multi-threaded CPU core, a DMA engine, a memory mapped peripheral, etc. For example, software instructions can be used to set a read monitor indicator for a block of cache memory for a particular hardware thread. If another hardware thread writes to the memory block, t...
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A computing system includes a number of threads. The computing system is configured to allow for monitoring and testing memory blocks in a cache memory to determine effects on memory blocks by various agents. The system includes a processor. The processor includes a mechanism implementing an instruction set architecture including instructions accessible by software. The instructions are configured to: set per-hardware-thread, for a first thread, memory access monitoring indicators for a plurality of memory blocks, and test whether any monitoring indicator has been reset by the action of a conflicting memory access by another agent. The processor further includes mechanism configured to: detect conflicting memory accesses by other agents to the monitored memory blocks, and upon such detection of a conflicting access, reset access monitoring indicators corresponding to memory blocks having conflicting memory accesses, and remember that at least one monitoring indicator has been so reset.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is related to U.S. patent application Ser. No. ______ filed Jun. 26, 2009, Docket No. 13768.1209, and entitled “PERFORMING ESCAPE ACTIONS IN TRANSACTIONS”, as well as U.S. application Ser. No. ______, filed Jun. 26, 2009, Docket No. 13768.1211, and entitled “WAIT LOSS SYNCHRONIZATION”, as well as U.S. application Ser. No. ______, filed Jun. 26, 2009, DOCKET NO. 13768.1208, and entitled “MINIMIZING CODE DUPLICATION IN AN UNBOUNDED TRANSACTIONAL MEMORY”, as well as U.S. application Ser. No. ______, filed Jun. 26, 2009, Docket No. 13768.1213, and entitled “PRIVATE MEMORY REGIONS AND COHERENCE OPTIMIZATIONS”, as well as U.S. application Ser. No. ______, filed Jun. 26, 2009, Docket No. 13768.1214, and entitled “OPERATING SYSTEM VIRTUAL MEMORY MANAGEMENT FOR HARDWARE TRANSACTIONAL MEMORY”, as well as U.S. application Ser. No. ______, filed Jun. 26, 2009, Docket No. 13768.1215, and entitled “METAPHYSICALLY ADDRESSED CACHE METADA...
Claims
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IPC IPC(8): G06F12/08
CPCG06F11/362G06F12/0815
Inventor GRAY, JANCALLAHAN, DAVIDSMITH, BURTON JORDANSHEAFFER, GADADL-TABATABAI, ALI-REZABASSIN, VADIMGEVA, ROBERT Y.
Owner MICROSOFT TECH LICENSING LLC