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Pseudo-orthogonal code generator

a generator and pseudo-orthogonal technology, applied in the field of pseudo-orthogonal pseudo-orthogonal pseudo-orthogonal pseudo-orthogonal pseudo-orthogonal pseudo-orthogonal pseudo-orthogonal pseudo-orthogonal pseudo-orthogonal pseudo-orthogonal pseudo-orthogonal pseudo-orthogonal pseudo-orthogonal pseudo-orthogonal pseudo-orthogonal pseudo-orthogonal

Active Publication Date: 2011-05-12
KOREA ELECTRONICS TECH INST
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0003]This following description relates to a pseudo-orthogonal code generator, and more particularly, to a pseudo-orthogonal code generator that minimizes the complexity of a pseudo-orthogonal code generator and improves the operating speed in a radio transmitting system using pseudo-orthogonal codes.

Problems solved by technology

Thus, the efficiency of the transmission channel is deteriorated due to an extremely low spectral efficiency of no more than 0.25( 4 / 16).
Thus, the configuration is very complicated and the overall size becomes larger due to the much enlarged gate area when the pseudo-orthogonal code generator is fabricated as an application specific integrated circuit (ASIC).
In addition to the above problem, there is a disadvantage of a slower operating speed because it uses a ROM.

Method used

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Embodiment Construction

[0021]The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and / or systems described herein. Accordingly, various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described herein will be suggested to those of ordinary skill in the art. Also, descriptions of well-known functions and constructions may be omitted for increased clarity and conciseness.

[0022]FIG. 2 illustrates an example of a pseudo-orthogonal code generator. Referring to FIG. 2, the example pseudo-orthogonal code includes a serial-to-parallel converter 10, a combined circuit unit 100, and a 4-bit counter 200.

[0023]The serial-to-parallel converter 10 converts transmitting data that is serially inputted in single bits into a 9-bit parallel data. The 4-bit counter 200 repeatedly counts from 0 to 15. The combined circuit unit 100 sequentially generates 16-bit pseudo-orthogonal codes using the 9-bit paralle...

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Abstract

A pseudo-orthogonal code generator is provided. The pseudo-orthogonal code generator simplifies overall configuration and provides a more efficient operating speed by implementing a pseudo-orthogonal code generator using combined circuits instead of using a read only memory (ROM) circuit. The pseudo-orthogonal code generator reduces its overall size by reducing gate area.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit under 35 U.S.C. §119(a) of a Korean Patent Application No. 10-2009-0107639 filed Nov. 9, 2009 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.BACKGROUND[0002]1. Field[0003]This following description relates to a pseudo-orthogonal code generator, and more particularly, to a pseudo-orthogonal code generator that minimizes the complexity of a pseudo-orthogonal code generator and improves the operating speed in a radio transmitting system using pseudo-orthogonal codes.[0004]2. Description of the Related Art[0005]Table 1 is a Walsh-Hardamard code table that is used in a conventional orthogonal coding method. For example, in a conventional orthogonal code generator receiving four binary signal inputs, the total number of orthogonal codes that a bit row can have from these inputs are 16(=24). In this example, the length of each ort...

Claims

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Application Information

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IPC IPC(8): H04J13/00H03M9/00
CPCH04J13/10H04L27/32
Inventor KIM, YONGSEONGSEO, KYEUNGHAKCHO, JINWOONGLEE, HYUNSEOKKWON, TAIGILLIM, YONGSEOK
Owner KOREA ELECTRONICS TECH INST