Facilitating quiesce operations within a logically partitioned computer system

Abstract

A facility is provided for processing to distinguish between a full conventional (or total system) quiesce request within a logically partitioned computer system, which requires all processors of the computer system to remain quiesced for the duration of the quiesce-related operation, and a new early-release conventional quiesce request, which is associated with fast-quiesce request utilization. In accordance with the facility, once all processors have quiesced responsive to a pending quiesce request sequence, the processors are allowed to block early-release conventional quiesce interrupts and to continue processing if there is no total system quiesce request in the pending quiesce request sequence.

Description

BACKGROUND[0001]This invention relates, in general, to facilitating request processing within a logically partitioned computing system, and more particularly, to facilitating quiesce request processing within a logically partitioned computer system.[0002]The processing of a request by one processor may affect one or more other processors of a computer system. For example, in a Symmetric Multi-Processor (SMP) system based on the z / Architecture® of International Business Machines Corporation, Armonk, N.Y., various broadcast purge operations, such as Invalidate Page Table Entry (IPTE), Invalidate DAT Table Entry (IDTE), Set Storage Key Extended (SSKE), and Compare and Swap and Purge (CSP) instructions, require entries of one or more buffers (e.g., Translation Lookaside Buffers (TLBs)) to be removed from the buffers in all processors of the computing environment. Furthermore, the architecture requires the buffers to be purged atomically, such that no processor can observe a new TLB entr...

AI Technical Summary

Benefits of technology

[0043]The native processor typically executes emulation software comprising either firmware or a native operating system to perform emulation of the emulated processor. The emulation software is responsible for fetching and executing instructions of the emulated processor architecture. The emulation software maintains an emulated program counter to keep track of instruction boundaries. The emulation software may fetch one or more emulated machine instructions at a time and convert the one or more emulated machine instructions to a corresponding group of native machine instructions for execution by the native processor. These converted instructions may be cached such that a faster conversion can be accomplished. Notwithstanding, the emulation software is to maintain the architecture rules of the emulated processor architecture so as to assure operating systems and applications written for the emulated processor operate correctly. Furthermore, the emulation software is to provide resources identified by the emulated processor architecture including, but not limited to, control registers, general purpose registers, floating point registers, dynamic address translation function including segment tables and page tables for example, interrupt mechanisms, context switch mechanisms, Time of Day (TOD) clocks and architected interfaces to I / O subsystems such that an operating system or an application program designed to run on the emulated processor, can be run on the native processor having the emulation software.

Problems solved by technology

Furthermore, the architecture requires the buffers to be purged atomically, such that no processor can observe a new TLB entry, while some other processor observes an old entry.

In particular, it is common that one processor may be executing a long running instruction that is not interruptible, so that it cannot reach the quiesce state for a period of time, and other processors are required to wait for this one processor to reach the quiesce state before the steps described above can be completed.

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