PCI express tlp processing circuit and relay device provided with this

a relay device and processing circuit technology, applied in the field of pci express devices, can solve the problem that errors cannot be detected at the reception destination of tlps
US20120030402A1Inactive Publication Date: 2012-02-02KK TOSHIBA
6 Cites 12 Cited by

Patent Information

Authority / Receiving Office
US · United States
Current Assignee / Owner
KK TOSHIBA
Publication Date
2012-02-02
Estimated Expiration
Not applicable · inactive patent

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

A PCI Express TLP processing circuit (10) comprises: a plurality of reception processing sections (2a1); a transmission processing section (2b); and a multiplexer (2c1) that performs transmission to the transmission processing section, selecting one of the reception processing sections; and at least a reception processing section comprises: a redundancy code generating circuit (12); an LCRC / sequential number detection circuit (13); a buffer memory (14); a packet control circuit section (16) that controls transmission for normal transmission to the transmission destination of the TLP in question or for nullifying transmission; and the transmission processing section comprises: a sequential number generating circuit (19); an LCRC generating circuit (20) and a relay circuit error detection circuit (21), whereby data integrity of the transmitted TLP can be guaranteed.
Need to check novelty before this filing date? Find Prior Art

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims benefit of priority from Japanese application number JP2009-100756 filed Apr. 17, 2009; the entire contents of which are incorporated by reference herein.TECHNICAL FIELD

[0002] The present invention relates to a PCI Express device and in particular to a processing circuit of transaction layer packets (TLP).BACKGROUND ART

[0003] A PCI Express (registered trademark) bus is a high-speed serial interface employing point-to-point connection that has been developed in recent years for transferring data in computer systems and other electronic devices; the occupied area of the substrate of the bus is less than in the case of conventional parallel transfer, making possible further miniaturisation, and application of this technique in many fields is being studied.

[0004] The details of the standard have been laid down as the PCI Express Base Specification by the PCI-SIG (Peripheral Component Interconnect-Special Interest Group), w...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More