PCI express tlp processing circuit and relay device provided with this

Abstract

A PCI Express TLP processing circuit (10) comprises: a plurality of reception processing sections (2a1); a transmission processing section (2b); and a multiplexer (2c1) that performs transmission to the transmission processing section, selecting one of the reception processing sections; and at least a reception processing section comprises: a redundancy code generating circuit (12); an LCRC / sequential number detection circuit (13); a buffer memory (14); a packet control circuit section (16) that controls transmission for normal transmission to the transmission destination of the TLP in question or for nullifying transmission; and the transmission processing section comprises: a sequential number generating circuit (19); an LCRC generating circuit (20) and a relay circuit error detection circuit (21), whereby data integrity of the transmitted TLP can be guaranteed.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims benefit of priority from Japanese application number JP2009-100756 filed Apr. 17, 2009; the entire contents of which are incorporated by reference herein.TECHNICAL FIELD[0002]The present invention relates to a PCI Express device and in particular to a processing circuit of transaction layer packets (TLP).BACKGROUND ART[0003]A PCI Express (registered trademark) bus is a high-speed serial interface employing point-to-point connection that has been developed in recent years for transferring data in computer systems and other electronic devices; the occupied area of the substrate of the bus is less than in the case of conventional parallel transfer, making possible further miniaturisation, and application of this technique in many fields is being studied.[0004]The details of the standard have been laid down as the PCI Express Base Specification by the PCI-SIG (Peripheral Component Interconnect-Special Interest Group), w...

AI Technical Summary

Benefits of technology

[0055]According to the present invention, a PCI Express TLP processing circuit and a relay device provided there with can be provided whereby data integrity can be guaranteed by detecting an error in data transmitted from a relay device.

Problems solved by technology

Consequently, if reliance for data error detection is placed exclusively on the LCRC function, there is the problem that, if an error is generated in the data of a TLP in a relay circuit (in this case, any circuit that is located above the data-link layer is termed a relay circuit) of the switch or the root complex, since an LCRC including this error is generated normally, this error cannot be detected at the reception destination of the TLP.

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