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Techniques for metal gate workfunction engineering to enable multiple threshold voltage finfet devices

a technology of finfet and gate work, which is applied in the direction of basic electric elements, semiconductor devices, electrical equipment, etc., can solve the problems of multiple threshold voltage (vt) devices, aggressively scaled devices have serious drawbacks, and require a substantial amount of process complexity

Active Publication Date: 2014-03-06
GLOBALFOUNDRIES US INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

The present invention provides techniques for improving the function of gate electrodes in FIN field-effect transistor (FET) devices. This is achieved by depositing a work function setting material that is proportional to the spacing between the fins in the device. This material can be used to set the threshold voltage of the device, which can affect its overall performance. By controlling the amount of material deposited, the invention allows for the fabrication of FET devices with improved performance and reliability.

Problems solved by technology

One key problem with undoped devices is the implementation of multiple threshold voltage (Vt) devices.
To do so, however, for aggressively scaled devices has serious drawbacks from random dopant fluctuation (RDF) effects.
This however requires a substantial amount of process complexity.

Method used

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  • Techniques for metal gate workfunction engineering to enable multiple threshold voltage finfet devices
  • Techniques for metal gate workfunction engineering to enable multiple threshold voltage finfet devices
  • Techniques for metal gate workfunction engineering to enable multiple threshold voltage finfet devices

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Embodiment Construction

[0022]As described above, there are notable disadvantages associated with using doping and / or different work function gate stacks to produce multiple threshold voltage (Vt) FIN field-effect transistor (FET) devices. Advantageously, provided herein are techniques for producing multiple Vt FINFET devices using a work function setting material in an amount that is continuously modulated as a function of FIN pitch. Namely, a thickness of the materials in the device gate stacks will be chosen such that less work function setting material ends up in the tighter pitch FINFETs. Thus, for smaller pitch, higher FINFET Vt is obtained and therefore, through FIN pitch variation, different Vt devices may be fabricated. The technique does come at the cost of FIN active width density, however if the lower Vt (wider FIN pitch) devices are not used for a large fraction of the chip area, this trade-off may be very preferred over the use of more complex (and yield challenging) integration schemes.

[0023...

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Abstract

Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a FIN FET device is provided. The FIN FET device includes a SOI wafer having an oxide layer and a SOI layer over a BOX, and a plurality of fins patterned in the oxide layer and the SOI layer; an interfacial oxide on the fins; and at least one gate stack on the interfacial oxide, the gate stack having (i) a conformal gate dielectric layer present, (ii) a conformal gate metal layer, and (iii) a conformal work function setting material layer. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer present in the gate stack is proportional to a pitch of the fins.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)[0001]This application is a continuation of U.S. application Ser. No. 13 / 596,687 filed on Aug. 28, 2012, the disclosure of which is incorporated by reference herein.FIELD OF THE INVENTION[0002]The present invention relates to FIN field-effect transistor (FET) devices, and more particularly, to techniques for gate work function engineering using a work function setting material an amount of which is provided proportional to fin pitch so as to enable multiple threshold voltage devices.BACKGROUND OF THE INVENTION[0003]In current complementary metal-oxide semiconductor (CMOS) scaling, the use of undoped FIN field-effect transistor (FET) devices is highly preferred as a device choice for CMOS at and beyond the 22 nanometer (nm) node. One key problem with undoped devices is the implementation of multiple threshold voltage (Vt) devices. One solution is to dope the FINFET device. To do so, however, for aggressively scaled devices has serious drawback...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L27/12
CPCH01L21/845H01L27/1211
Inventor CHANG, JOSEPHINE B.LAUER, ISAACLIN, CHUNG-HSUNSLEIGHT, JEFFREY W.
Owner GLOBALFOUNDRIES US INC
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