Efficient validation of coherency between processor cores and accelerators in computer systems

Abstract

A method of testing cache coherency in a computer system design allocates different portions of a single cache line for use by accelerators and processors. The different portions of the cache line can have different sizes, and the processors and accelerators can operate in the simulation at different frequencies. The verification system can control execution of the instructions to invoke different modes of the coherency mechanism such as direct memory access or cache intervention. The invention provides a further opportunity to test any accelerator having an original function and an inverse function by allocating cache lines to generate an original function output, allocating cache lines to generate an inverse function output based on the original function output, and verifying correctness of the original and inverse functions by comparing the inverse function output to the original function input.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application is a continuation of copending U.S. patent application Ser. No. 13 / 770,711 filed Feb. 19, 2013.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention generally relates to computer systems, and more particularly to a method of verifying the design of a computer system having a resource such as a cache memory which is shared among multiple devices such as processors and accelerators.[0004]2. Description of the Related Art[0005]When a new computer system (or subsystem) is designed, it is important to ensure that the design is going to work properly before proceeding with fabrication preparation for the integrated circuit devices making up the system, and their assembly into the finished product. A variety of tests can be performed to evaluate the design, but simulation remains the dominant strategy for functionally verifying high-end computer systems. A design-under-test is driven by vectors of ...

AI Technical Summary

Benefits of technology

This patent is about a method for testing a system design that has a shared resource, such as a cache memory. The method involves selecting a portion of the shared resource for testing, allocating it for use by a processor and an accelerator, executing instructions using that allocated portion, and verifying the correctness of the data stored in it. This method allows for testing any accelerator that has both an original function and an inverse function by allocating cache lines for both functions and comparing the outputs. The technical effects of this invention include improved efficiency and accuracy in testing system designs with shared resources.

Problems solved by technology

Higher-level caches can store a much larger amount of information (program instructions and operand data) than the on-board caches can, but at a longer access penalty.

There are many, more complicated protocols which expand upon the MESI protocol.

Images