Package-on-package assembly and method for manufacturing the same

Abstract

A package-on-package assembly includes a bottom die package and a top die package mounted on the bottom die package. The bottom die package includes an interposer having a first side and a second side opposite to the first side; at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps; at least one TSV chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, wherein the TSV chip comprises at least one TSV connecter and is mounted on the first side through a plurality of second bumps arranged within the peripheral area; a molding compound disposed on the first side, the molding compound covering the at least one active chip and the at least one TSV chip; and a plurality of solder bumps mounted on the second side.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates generally to the field of semiconductor packaging, and more particularly to a Package-on-Package (PoP) assembly and a method for manufacturing the same.[0003]2. Description of the Prior Art[0004]With recent advancements in the semiconductor manufacturing technology microelectronic components are becoming smaller and circuitry within such components is becoming increasingly dense. To reduce the dimensions of such components, the structures by which these components are packages and assembled with circuit boards must become more compact. In order to meet the requirements of smaller footprints with higher densities, 3D stacking packaging such as PoP (Package-on-Package) assembly has been developed.[0005]A PoP assembly typically includes a top package with a device die bonded to a bottom package with another device die. In PoP designs, the top package may be interconnected to the bottom package...

AI Technical Summary

Benefits of technology

[0034]It is advantageous to use the invention because most of the peripheral area 104 around the chip mounting area 102 is occupied by the TSV chips 420b, the used amount of the molding compound 500 is reduced, and therefore the warpage of the wafer or die package is alleviated or avoided.

Problems solved by technology

With recent advancements in the semiconductor manufacturing technology microelectronic components are becoming smaller and circuitry within such components is becoming increasingly dense.

However, the prior art PoP assembly is not able to provide very tight pitch stacking.

Further, the prior art PoP assembly has large package form factor and poor warpage control.

The thick layer of the molding compound results in increased warping of the packaging due to coefficient of thermal expansion (CTE) mismatch, and the thickness of the packaging.

Warpage can prevent successful assembly of a die-to-wafer stack because of the inability to maintain the coupling of the die and wafer.

Warpage issue is serious especially in a large sized wafer, and has raised an obstacle to a wafer level semiconductor packaging process that requires fine-pitch RDL process.

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