Conductively doped polymer pattern placement error compensation layer

Abstract

A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The disclosed subject matter relates generally to the fabrication of semiconductor devices and, more particularly, to forming a pattern placement error compensation layer.[0003]2. Description of the Related Art[0004]In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and / or power consumption and / or diversity of circuit functions. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines and the spaces between the metal lines have to be reduced to compensate for a reduced amount ...

AI Technical Summary

Benefits of technology

The conductive polymer layer effectively reduces the impact of pattern placement errors by providing a conductive path for current flow, maintaining electrical isolation between features and improving device performance by reducing contact resistance.

Problems solved by technology

One consequence of the off-axis illumination angle is telecentricity and shadowing errors which manifest as a pattern shift relative to the mask.

An absolute pattern shift can compromise process margins by misaligning connections.

However, the overlap area is compromised when pattern shift occurs, which may result in a degradation in device performance.

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