Source and Drain Isolation for CMOS Nanosheet with One Block Mask

Abstract

Techniques for source / drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial / active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET / NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET / NFET stacks to expose tips of the active channel nanosheets in the PFET / NFET stacks; forming inner spacers alongside the PFET / NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET / NFET stacks. A nanosheet device is also provided.

Description

FIELD OF THE INVENTION[0001]The present invention relates to complementary metal oxide semiconductor (CMOS) nanosheet devices, and more particularly, to techniques for source and drain isolation in CMOS nanosheet devices.BACKGROUND OF THE INVENTION[0002]Complementary metal oxide semiconductor (CMOS) nanosheet devices include a vertical stack of channel layers interconnecting a source and a drain. Advantageously, CMOS nanosheet devices can employ gate-all-around (GAA) designs since the channel layers are anchored at either end by the source and drain.[0003]A drawback with current nanosheet device designs, however, is that the epitaxy growth process used to form the source and drains can cause parasitic growth on the underlying substrate. This parasitic growth can undesirably cause shorts between source and drain.[0004]Thus, improved nanosheet device fabrication techniques would be desirable.SUMMARY OF THE INVENTION[0005]The present invention provides techniques for source and drain i...

AI Technical Summary

Benefits of technology

The present invention provides techniques for isolating the source and drain of CMOS nanosheet devices. A method is provided to form the devices, which includes patterning the nanosheets into PFET and NFET stacks, and subsequently recessing the sacrificial nanosheets to expose the tips of the active channel nanosheets. An oxide protective layer is then lining the pockets in the substrate, and selectively etching back the inner spacers to expose the tips of the active channel nanosheets. The invention also includes the nanosheet device, which includes individual PFET and NFET stacks, pockets in the substrate, an oxide protective layer, epitaxial source and drains, gates surrounding at least a portion of each of the active channel nanosheets, and inner spacers offsetting the gates from the epitaxial source and drains. The technical effects of the invention include improved source and drain isolation, reduced leakage current, and improved device performance.

Problems solved by technology

A drawback with current nanosheet device designs, however, is that the epitaxy growth process used to form the source and drains can cause parasitic growth on the underlying substrate.

This parasitic growth can undesirably cause shorts between source and drain.

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