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Semiconductor package structure, semiconductor wafer level package and semiconductor manufacturing process

a semiconductor and package technology, applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical devices, etc., can solve the problems of warpage of semiconductor package structures, and risk of peeling situations

Active Publication Date: 2020-05-07
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text describes a semiconductor package structure and a manufacturing process for it. The structure includes a semiconductor die with an active surface, wiring structures, an encapsulant, and conductive elements. The encapsulant is made of an encapsulating material with a specific stiffness. The conductive elements are embedded in the encapsulant and connected to the wiring structures. The technical effects of this structure and manufacturing process include improving the reliability and performance of semiconductor devices.

Problems solved by technology

However, warpage may occur to a thin semiconductor package structure.
A warpaged semiconductor package structure cannot be readily attached to a substrate, an interposer or a printed circuit board during a reflow process.
This creates a risk of a peeling situation.

Method used

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  • Semiconductor package structure, semiconductor wafer level package and semiconductor manufacturing process
  • Semiconductor package structure, semiconductor wafer level package and semiconductor manufacturing process
  • Semiconductor package structure, semiconductor wafer level package and semiconductor manufacturing process

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Embodiment Construction

[0034]Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0035]The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features, such that the fir...

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PUM

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Abstract

A semiconductor package structure includes a semiconductor die, at least one wiring structure, an encapsulant and a plurality of conductive elements. The semiconductor die has an active surface. The at least one wiring structure is electrically connected to the active surface of the semiconductor die. The encapsulant surrounds the semiconductor die. The encapsulant is formed from an encapsulating material, and a Young's Modulus of the encapsulant is from 0.001 GPa to 1 GPa. The conductive elements are embedded in the encapsulant, and are electrically connected to the at least one wiring structure.

Description

BACKGROUND1. Field of the Disclosure[0001]The present disclosure relates to a semiconductor package structure, a semiconductor wafer level package and a semiconductor manufacturing process, and more particularly to a semiconductor package structure including a soft encapsulant, a semiconductor wafer level package and a semiconductor manufacturing process.2. Description of the Related Art[0002]The trend for an electronic product is light, thin, short and small. The semiconductor package structures are designed toward to the above demand. However, warpage may occur to a thin semiconductor package structure. A warpaged semiconductor package structure cannot be readily attached to a substrate, an interposer or a printed circuit board during a reflow process. This creates a risk of a peeling situation.SUMMARY[0003]In some embodiments, according to an aspect, a semiconductor package structure includes a semiconductor die, at least one wiring structure, an encapsulant and a plurality of co...

Claims

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Application Information

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IPC IPC(8): H01L23/29H01L23/498H01L21/56H01L21/48H01L23/31
CPCH01L21/4853H01L21/561H01L23/295H01L23/3128H01L23/49822H01L23/49816H01L24/16H01L2224/16227H01L23/3185H01L23/49838H01L23/49811H01L23/5389H01L24/19H01L24/20H01L24/96H01L2224/131H01L2224/16237H01L2224/2919H01L2224/32225H01L2224/96H01L2924/18161H01L2924/00014H01L2224/19
Inventor CHEN, DAO-LONGHUNG, CHIH-PINCHEN, MING-HUNG
Owner ADVANCED SEMICON ENG INC