Phase-change random access memory (PRAM) write disturb mitigation

Abstract

A method for writing memory cells including: applying a program voltage to a target wordline; grounding bitlines of memory cells to be written to a first resistance state; setting a bitline voltage of unselected bitlines; and setting a wordline voltage of unselected wordlines; applying the program voltage to a target bitline; grounding wordlines of the memory cells to be written to a second resistance state; setting the wordline voltage of the unselected wordlines to a first value if a peak of a maximum voltage drop is greater than or equal to a second value; otherwise, setting the wordline voltage to zero; and setting the bitline voltage of the unselected bitlines to a third value if the peak of the maximum voltage drop is greater than or equal to the second value; otherwise, setting the bitline voltage to zero.

Description

TECHNICAL FIELD[0001]Exemplary embodiments of the present inventive concept relate to write methods of nonvolatile memory devices, and more particularly, to a nonvolatile memory device write method with reduced write disturbs.DISCUSSION OF RELATED ART[0002]Phase-change random access memory (PRAM) has improved scaling potential compared to traditional memory technologies. In order to obtain small feature size and enable capacity through vertical stacks, proper vertical three-dimensional architecture is required. Cross-point structures, where separate wordline and bitline wire bars (or planes as in V-PRAM) are connected with variable-resistance materials, are able to exploit PRAM's inherent characteristics and take advantage of process vertical buildup while tolerating high temperatures. However, the cross-point construction raises reliability and power consumption challenges.[0003]Write disturb phenomenon occurs in cross-point formation when applying a write voltage for target cells....

AI Technical Summary

Benefits of technology

The present invention provides a method for writing memory cells in a nonvolatile memory device comprising wordlines overlapping bitlines. The method includes a set phase and a reset phase. In the set phase, a program pulse voltage is applied to a target wordline, while the bitlines of the memory cells are grounded and the wordline voltage of unselected wordlines is set to a first value. In the reset phase, the program pulse voltage is applied to a target bitline, while the wordline voltage of unselected wordlines is set to a second value. The method also includes setting the bitline voltage of unselected bitlines to a third value if the peak maximum voltage drop of memory cells is greater than or equal to a second value. The nonvolatile memory device is phase-change random access memory. The technical effect of the invention is to improve the efficiency and accuracy of writing memory cells in a nonvolatile memory device.

Problems solved by technology

However, the cross-point construction raises reliability and power consumption challenges.

However, corresponding cells that are located in the same bitline and unselected wordlines now have write potential in their bottom electrode, requiring their wordline voltage to be the same which leads to setting low-resistance in unselected cells.

In this case, nearly half of each wordline contains high-resistance cells and therefore about half of an array matrix would suffer from right disturb.

Images