Electronic package and method for fabricating the same

Abstract

An electronic package and a method for fabricating the same are provided. The electronic package includes a stepped recess formed at a peripheral portion of a packaging module to release stress of the electronic package.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority to Taiwan Application No. 109114552, filed on Apr. 30, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.BACKGROUND1. Technical Field[0002]The present disclosure relates to a packaging process, and more particularly, to a multichip electronic package and a method for fabricating the same.2. Description of Related Art[0003]With the rapid development of the electronic industry, electronic products are trending towards multiple functions and high performance. In order to meet the requirement for miniaturization of the electronic packages, a wafer level packaging (WLP) technique has been developed.[0004]FIGS. 1A to 1E are cross-sectional views illustrating a method for fabricating a semiconductor package 1 using a conventional wafer level packaging technique.[0005]As shown in FIG. 1A, a thermal release tape 100 is forme...

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Benefits of technology

[0023]As can be understood from the above, the electronic package of the present disclosure and the method for fabricating the same allow stress to be released at the time of singulation as a result of the recess formed on the packaging layer at the peripheral portion of the packaging module. Compared to the prior art, the fabricating method of the present disclosure improves warpage caused by factors such as thermal processes and reliability test, thereby effectively strengthening the electronic package.

Problems solved by technology

However, in the fabrication process of the conventional semiconductor package 1, the carrier 10 occupies the entire layout (i.e., the mass production size), and the semiconductor components 11 are only provided on one side of the carrier 10, so after the encapsulant 14 is formed, a mismatch in the coefficients of thermal expansion between the semiconductor components 11 and the encapsulant 14 easily causes uneven distribution of thermal stress and warpage of the encapsulant 14 during a thermal cycle and, in turn, resulting in issues such as detachment of the solder balls (i.e., the conductive components 17) or non-wetting of the conductive components 17.

Moreover, warpage may also make it difficult to place the structure being manufactured inside the machine or cause the semiconductor components 11 to crack, which lowers the production yield.

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