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Handling and fusing load instructions in a processor

Active Publication Date: 2022-02-17
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach enhances processing efficiency by enabling the simultaneous execution of fusible load instructions, reducing delays, and improving overall system performance by optimizing the use of execution units and register files.

Problems solved by technology

Processors currently used in data processing systems process more than one instruction at a time, and often process those instructions out-of-order.

Method used

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  • Handling and fusing load instructions in a processor
  • Handling and fusing load instructions in a processor
  • Handling and fusing load instructions in a processor

Examples

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Embodiment Construction

[0019]The following description is made for illustrating the general principles of the invention and is not meant to limit the inventive concepts claimed herein. In the following detailed description, numerous details are set forth in order to provide an understanding of the computer system, computer architectural structure, processor, register files, accumulator register files, and their method of operation, however, it will be understood by those skilled in the art that different and numerous embodiments of the computer system, computer architectural structure, processor, register files, accumulator register files, and their method of operation can be practiced without those specific details, and the claims and invention should not be limited to the system, assemblies, subassemblies, embodiments, features, processes, methods, aspects, and / or details specifically described and shown herein. Further, particular features described herein can be used in combination with other describe...

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Abstract

A system, processor, and / or technique configured to: determine whether two or more load instructions are fusible for execution in a load store unit as a fused load instruction; in response to determining that two or more load instructions are fusible, transmit information to process the two or more fusible load instructions into a single entry of an issue queue; issue the information to process the two or more fusible load instructions from the single entry in the issue queue as a fused load instruction to the load store unit using a single issue port of the issue queue, wherein the fused load instruction contains the information to process the two or more fusible load instructions; execute the fused load instruction in the load store unit; and write back data obtained by executing the fused load instruction simultaneously to multiple entries in the register file.

Description

BACKGROUND OF INVENTION[0001]The present invention generally relates to data processing (information handling) systems, processors, processor pipelines, and methods of handling load instructions in systems and / or processors.[0002]Processors currently used in data processing systems process more than one instruction at a time, and often process those instructions out-of-order. In modern computer architecture, there are several known ways to design a computer adapted to perform more than one instruction at a time, or at least in the same time frame, including for example, using multiple execution slices within a processor core to process multiple instruction threads at the same time, with the threads sharing certain resources of the processor core. An execution slice may refer to multiple data processing hardware units connected in series like a pipeline within a processor to process multiple instructions in a single processing cycle. Pipelining involves processing instructions in sta...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F9/30G06F9/52G06F9/38
CPCG06F9/30043G06F9/3853G06F9/3802G06F9/52G06F9/30181G06F9/3836
Inventor LLOYD, BRYANTHOMPTO, BRIAN W.NGUYEN, DUNG Q.LEVENSTEIN, SHELDON BERNARDBARRICK, BRIAN D.ZOELLIN, CHRISTIAN GERHARD
Owner INT BUSINESS MASCH CORP