Static random-access memory (SRAM) array circuits including bilateral well tap cells with reduced width folded finger structure

Abstract

An SRAM array circuit in which a horizontal N-well of a well tap cell in a first row separated from a horizontal N-well of a well tap cell in a second row by a P-type substrate region is disclosed. The well tap cells include a bilateral P-type well tap disposed in the P-type substrate region between the horizontal N-wells in the first and second rows providing ground voltage to the P-type substrate on both sides of a column of well tap cells in the SRAM array circuit, rather than one P-type well tap for each side. Well tap cells without a vertical N-well reduces width, which corresponds to a reduction in width of the SRAM array circuit. The bilateral P-type well tap in a P-type implant region may include a plurality of folded fingers providing the ground voltage to the P-type substrate.

Description

BACKGROUNDI. Field of the Disclosure[0001]The field of the disclosure relates generally to integrated circuits (ICs) and more specifically to arrays of memory devices in an IC.II. Background[0002]Consumer electronics require a high level of performance at a low cost. Much of the performance is provided by integrated circuits (ICs). One way to lower cost in an IC is to reduce the area of the IC without reducing its performance. A large percentage of the area in many ICs is occupied by memory circuits. Therefore, a reduction in the size of memory circuits can be a significant contribution to a reduction in size and cost of an IC. Static random-access memory (SRAM) circuits are frequently used memory circuits due to their fast access time and long life. SRAM circuits includes several transistors formed in a semiconductor substrate. The transistors are arranged in efficient patterns in memory bit cells and the memory bit cells are arranged in two-dimensional (2D) arrays on the semicondu...

AI Technical Summary

Benefits of technology

The patent is about a new design for a type of memory cell called "well tap cell." The new design uses a special type of structure called a "bilateral P-type well tap" which provides a more efficient and cost-effective solution. By using this design, the memory cell can have a smaller width and a reduced number of components, which results in a more compact and cost-effective memory device. This new design also helps to maintain the performance of the memory device. Overall, this new design provides a more efficient and cost-effective solution for a memory device.

Problems solved by technology

Static random-access memory (SRAM) circuits are frequently used memory circuits due to their fast access time and long life.

Such voltage anomalies can trigger parasitic transistors in the semiconductor substrate structure to be conductive, resulting in a condition known as latch-up.

The current flow resulting from a latch-up condition can destroy the SRAM circuit.

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