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Memory unit, array and operation method thereof

a memory unit and array technology, applied in the field of memory units and arrays, can solve the problems of difficult to be the driving element of the memory cell, low breakdown voltage of the oxide layer, and very thin electrodes of the nmos transistor, etc., to achieve the effect of increasing the operation voltage, prolonging the product life cycle, and increasing reliability

Active Publication Date: 2022-10-27
MACRONIX INT CO LTD
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  • Claims
  • Application Information

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Benefits of technology

The present patent uses a P-type driving element to drive the memory cell, which increases the product life cycle and reliability under higher operation voltage. This means that the memory unit can have a longer lifespan and be more reliable.

Problems solved by technology

However, when the process technology reaches the technical level of, for example, 14 nm, the gate electrode of the NMOS transistor is very thin and the breakdown voltage of the oxide layer is too low, making it difficult to be the driving element of the memory cell.
However, due to the NMOS transistor as the driving element, it cannot withstand higher write times in the write operations with a voltage of 2.4V.
Therefore, the current configuration cannot increase the times of write operation and the product life cycle cannot be increased.

Method used

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  • Memory unit, array and operation method thereof
  • Memory unit, array and operation method thereof
  • Memory unit, array and operation method thereof

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Embodiment Construction

[0024]FIG. 1A shows a schematic diagram of a cross-sectional structure of a phase change memory unit according to one embodiment of the disclosure. As shown in FIG. 1A, the memory unit 100 comprises a memory cell (such as a variable resistor element) 102 and a driving element 104. In this embodiment, the memory cell 102 is made of phase change material but not limited thereto, and the driving element 104 may be a switching element, such as bipolar junction transistor (BJT), metal oxide semiconductor (MOS) transistor, field effect transistor (FET), diode, etc. In the embodiment, the driving element 104 is a P-type driving element, and a PMOS transistor is used as an example in the following description.

[0025]As shown in the cross-sectional view of FIG. 1, the memory unit 100 includes a PMOS transistor 104 with source-drains 104a, 104b and a gate 104c formed on a semiconductor substrate 106. In a memory array, a row of memory units 100 are connected by a word line WL, and the word lin...

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Abstract

A memory unit, array and operation method thereof are provided. The memory unit includes at least one P-type driver having a first end coupled to a power source, a second end and a control end coupled to a word line; a memory cell having a first end coupled to the second end of the P-type driver, and a second end coupled to a bit line.

Description

TECHNICAL FIELD[0001]The present invention relates to a memory unit, an array, and an operation method thereof.DESCRIPTION OF RELATED ART[0002]Phase change memory (PCM) uses changes in the phase of a material to achieve the characteristics of the memory. The phase change memory has the characteristics of small size and long storage time, and can also match the current semiconductor manufacturing technology.[0003]In the current phase change memory structure, an NMOS transistor is usually used as the transistor of the driving element of each memory cell. However, when the process technology reaches the technical level of, for example, 14 nm, the gate electrode of the NMOS transistor is very thin and the breakdown voltage of the oxide layer is too low, making it difficult to be the driving element of the memory cell. Under the existing configuration, writing data to the memory cell requires applying a voltage of about 2.4V to the word line and about 2.5V to the bit line. However, due t...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L27/24H01L27/11507H01L27/22G11C11/16G11C11/22G11C13/00H10B53/30
CPCH01L27/2436H01L27/11507H01L27/228G11C11/1659G11C11/1675G11C11/1673G11C11/2259G11C11/2275G11C11/2273G11C13/003G11C13/0069G11C13/004G11C2213/79G11C11/4074G11C16/14G11C13/0004G11C13/0007H10B63/30H10B61/22H10N70/231H10N70/826H10B53/30
Inventor HO, HSIN-YILUNG, HSIANG-LAN
Owner MACRONIX INT CO LTD
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