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System controller with Integrated low latency memory using non-cacheable memory physically distinct from main memory

a system controller and memory technology, applied in the field of memory subsystems, can solve the problems of increasing the relative degree of latency of these types of computer systems, slowing down the computer system, and affecting the performance of the system

Inactive Publication Date: 2003-05-06
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Thus, when accessing main memory (after L1 and L2 cache misses), the computer system experiences a relative degree of latency.
A snoop operation requires at least one clock cycle to perform, thus adding to the relative degree of latency within these types of computer systems.
This results in a relatively slower computer system with relatively slower processing and reduced computer system throughput.
Operating such a computer system is relatively time consuming and costly.
Because these embedded peripherals lack the sophistication of the main processor (or, for that matter, most external peripherals), in current computer systems, the embedded peripheral cannot access the memory subsystem.
Providing this dedicated memory "off chip" adds latency to embedded peripheral's memory accesses and consumes valuable space within the computer system.
Additionally, the exclusivity of the dedicated memory decreases the versatility of the computer system.

Method used

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  • System controller with Integrated low latency memory using non-cacheable memory physically distinct from main memory
  • System controller with Integrated low latency memory using non-cacheable memory physically distinct from main memory
  • System controller with Integrated low latency memory using non-cacheable memory physically distinct from main memory

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Experimental program
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Embodiment Construction

5.1 Description of a First Embodiment

In FIG. 1, there is shown a computer system 1 comprising an embodiment of the present invention. Generally, FIG. 1 illustrates a computer system 1 comprising a processor 10, a system controller 50 with an integrated low latency memory 130, a peripheral device 30 and a main memory 100. The low latency memory 130 may be considered a subset of the address space primarily embodied in main memory 100 although within the computer system 1 it is physically distinct from the main memory 100. Unlike a cache, the low latency memory 130 is not intended to mirror any portion of main memory 100. Instead it represents a unique subset of the main memory. Accordingly, in the present invention, the low latency memory 130 is a unique component of the memory subsystem.

5.1.1 Processor

FIG. 1 illustrates a uni-processor computer system, although the present invention may be equally beneficial in multi-processor computer systems. The processor 10 may be any conventiona...

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Abstract

The present invention relates to a computer system comprising at least one requesting agent, a system controller and a memory subsystem comprising a main memory and a noncacheable subset of main memory physically distinct from the main memory.

Description

1. FIELD OF THE INVENTIONThe present invention relates generally to memory subsystems in electronic devices. More particularly, the present invention relates to reducing latency in memory subsystems.2. BACKGROUND OF THE INVENTIONComputer systems typically comprise at least one processor, a memory subsystem, at least one system controller and one or more peripherals (such as PCI devices) operably connected by various buses, including a host bus operably connected between the processor and the system controller. The processor may include an internal level one (L1) cache. The memory subsystem typically comprises system or main memory external to both the processor and the system controller and a level two (L2) cache internal to the system controller. Together, the L1 cache and the memory subsystem (L2 cache and main memory) comprise a memory hierarchy.The system controller includes logic for, in conjunction with the processor and peripheral devices, controlling the transfer of data and...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G06F12/08
CPCG06F12/0888G06F12/0835
Inventor MEYER, JAMES W.
Owner MICRON TECH INC