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Stacked chip scale package structure

a technology of stacking and chip scale, applied in the direction of semiconductor devices, electrical equipment, semiconductor/solid-state device details, etc., can solve the problems of die cracking, inability to adjust the direction of the upper chip, and inability to use the chip design widely

Inactive Publication Date: 2003-10-14
ASE ASSEMBLY & TEST SHANGHAI +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The primary object of the present invention is to provide a package structure having dummy die design to resolve the problem of die crack caused by wire bonding of suspended chip.
Another object of the present invention is to provide a multi-layer CSP structure capable of flexibly adjusting the size and installation direction of the upper chip.
Yet another object of the present invention is to provide a package structure capable of shortening the trace length on the substrate to enhance the electric performance thereof.

Problems solved by technology

This is because a chip of stacked CSP is very thin, wire bonding of suspended chip will certainly result in die crack.
This problem causes that existent chip design has not widespread application, and sometimes the direction of the upper chip cannot be adjusted due to layout difficulty of the substrate.

Method used

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  • Stacked chip scale package structure
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Experimental program
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Embodiment Construction

The present invention is characterized in that dummy dies are disposed below the suspended portion of an upper chip as a support during wire bonding to resolve the problem of die crack caused by wire bonding of suspended chip.

As shown in FIG. 4, in a stacked CSP structure 40, a lower chip 12 and an upper chip 14 are stacked on a substrate 10. Each interface is bonded with adhesive. The adhesive can be silver epoxy. A plurality of bonding pads 22 and 24 are disposed on the upper chip 14 and the lower chip 12, respectively. The size of the upper chip 14 is larger than that of the lower chip 12 along the direction without the bonding pads 22. Therefore, two side regions of the upper chip 14 are suspended relative to the lower chip 12. The bonding pads 22 and 24 are properly arranged two opposite sides of the upper chip 14 and the lower chip 12 so that the two rows of bonding pads 22 of the upper chip 14 are parallel to the two rows of bonding pads 24 of the lower chip 12.

In order to ov...

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PUM

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Abstract

The present invention provides a stacked chip scale package structure, wherein a lower chip and an upper chip are stacked on a substrate. Two rows of bonding pads are disposed on each of the upper and lower chips. The bonding pads on the upper and lower chips are parallel arranged. At least a dummy die is disposed below the suspended portion of the upper chip and at the side of the lower chip as a support during wire bonding. A gap is reserved between the dummy die and the lower chip. The present invention utilizes the design of dummy die to resolve the problem of die crack caused by wire bonding of suspended chip. Therefore, the present invention can flexibly adjust the size and installation direction of the upper chip to meet the requirement of substrate layout, and can also shorten the trace length on the substrate to enhance the electric performance thereof.< / PTEXT>

Description

The present invention relates to an integrated circuit (IC) package and, more particularly, to an improved chip stacked structure of stacked chip size / scale package (stacked CSP).As shown in FIGS. 1 and 2, in a chip stacked structure of stacked chip size / scale package (stacked CSP, or called multi-chip package, MCP), a lower chip 12 and an upper chip 14 are disposed on a substrate 10. Each interface is bonded together with adhesives 16 and 18. Gold wires 20 are used to connect bonding pads 22 and 24 on the upper and lower chips 14 and 12 to contacts 26 on the substrate 10. A plurality of solder balls 28 are provided below the substrate 10.In the prior art, the size of the lower chip is larger than that of the upper chip so as to limit the layout of the substrate. Even the size of the upper chip is larger than that of the lower chip, as shown in FIG. 3, in order to let the wire path be the shortest, the bonding pads of the upper and lower chips 14 and 12 are arranged in the same dire...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L25/065
CPCH01L25/0657H01L2224/32145H01L2224/45144H01L2924/15311H01L2924/01079H01L2225/06562H01L2225/06555H01L2225/0651H01L2224/48091H01L2224/48227H01L2224/73265H01L2924/00014H01L2924/00
Inventor PENG, YI-LIANGWU, KAI-CHIANG
Owner ASE ASSEMBLY & TEST SHANGHAI
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