Stacked chip scale package structure

a technology of stacking and chip scale, applied in the direction of semiconductor devices, electrical equipment, semiconductor/solid-state device details, etc., can solve the problems of die cracking, inability to adjust the direction of the upper chip, and inability to use the chip design widely
US6633086B1Inactive Publication Date: 2003-10-14ASE ASSEMBLY & TEST SHANGHAI +1
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Patent Information

Authority / Receiving Office
US ยท United States
Patent Type
Patents(United States)
Current Assignee / Owner
ASE ASSEMBLY & TEST SHANGHAI
Publication Date
2003-10-14
Estimated Expiration
Not applicable ยท inactive patent

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Abstract

The present invention provides a stacked chip scale package structure, wherein a lower chip and an upper chip are stacked on a substrate. Two rows of bonding pads are disposed on each of the upper and lower chips. The bonding pads on the upper and lower chips are parallel arranged. At least a dummy die is disposed below the suspended portion of the upper chip and at the side of the lower chip as a support during wire bonding. A gap is reserved between the dummy die and the lower chip. The present invention utilizes the design of dummy die to resolve the problem of die crack caused by wire bonding of suspended chip. Therefore, the present invention can flexibly adjust the size and installation direction of the upper chip to meet the requirement of substrate layout, and can also shorten the trace length on the substrate to enhance the electric performance thereof.< / PTEXT>
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Description

The present invention relates to an integrated circuit (IC) package and, more particularly, to an improved chip stacked structure of stacked chip size / scale package (stacked CSP).As shown in FIGS. 1 and 2, in a chip stacked structure of stacked chip size / scale package (stacked CSP, or called multi-chip package, MCP), a lower chip 12 and an upper chip 14 are disposed on a substrate 10. Each interface is bonded together with adhesives 16 and 18. Gold wires 20 are used to connect bonding pads 22 and 24 on the upper and lower chips 14 and 12 to contacts 26 on the substrate 10. A plurality of solder balls 28 are provided below the substrate 10.In the prior art, the size of the lower chip is larger than that of the upper chip so as to limit the layout of the substrate. Even the size of the upper chip is larger than that of the lower chip, as shown in FIG. 3, in order to let the wire path be the shortest, the bonding pads of the upper and lower chips 14 and 12 are arranged in the same dire...

Claims

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