In-situ electron beam induced current detection

Abstract

A method and in-situ sample current amplification system for carrying out failure analysis of integrated circuit semiconductor device conductive portions. The method includes providing an integrated circuit (IC) semiconductor device; providing a pre-amplifier board (PAB) comprising current signal amplification electronics; mounting the IC semiconductor device in electrical communication with the PAB; mounting the PAB comprising the IC semiconductor device in a scanning electron microscope (SEM) for probing the IC semiconductor device with a primary electron beam; exposing at least a portion of the IC semiconductor device to the primary electron beam to induce a current signal within the conductive portions; amplifying the current signal; and, outputting the amplified current signal to an image display system to produce an image representative of an electrical resistance of the conductive portions.

Description

FIELD OF THE INVENTION[0001]This invention generally relates to metrology techniques in micro-integrated circuit manufacturing and more particularly to an improved metrology method and sampling system for determining the integrity of micro-integrated circuitry in semiconductor devices by electron beam induced current detection and mapping.BACKGROUND OF THE INVENTION[0002]Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the difficult factors in the continuing evolution toward smaller device size and higher density has been the ability to consistently form small critical dimensions within predetermined error windows. For example, semiconductor feature sizes are frequently subjected to optical or electrical metrology inspections following photolithographic patterning and etching to ensure that critical dimensions are within acceptable limi...

AI Technical Summary

Problems solved by technology

One of the difficult factors in the continuing evolution toward smaller device size and higher density has been the ability to consistently form small critical dimensions within predetermined error windows.

A disadvantage of the EBIC methods of the prior art is that for ICs having overlying layers, the primary electron beam must have sufficient energy to penetrate through the passivation layer to reach the semiconductor device layer in the IC to create a detectable current on the order of about 1 micro-amp.

One problem with prior art methods including measuring electron beam induced currents is that a relatively long signal carrying lead is required to transport the signal from the sample to ex-situ measuring devices.

The limited sensitivity of prior art methods creates the need for high energy electron beams to create sufficient current signals which can cause dielectric breakdown and associated electron beam induced damage to the sample, for example by in-situ X-ray generation.

Further, as IC metal interconnects become smaller, the interconnect resistance increases, reducing the measurable electron beam induced current for a given electron accelerating voltage.

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