Method of forming a gate contact in a semiconductor device

Abstract

A processing sequence for definition of gate contacts can be implemented using either a deep ultra-violet (DUV) or mid ultra-violet (MUV) positive resist processing and supports the use of a reticle that integrates contacts to various regions including gates, sources and drains of various devices. In a one example, the wafer is coated with a planarizing anti-reflective coating (ARC), which then supports imaging of gate contacts using a positive DUV or MUV resist. This processing allows the nitride cap of certain transistor gates to be replaced with an oxide. In this example, the ARC can serve as an etch guide for selective removal of a film.

Description

TECHNICAL FIELD[0001]The present invention relates generally to semiconductor devices and more particularly to a method of forming a gate contact in a semiconductor device.BACKGROUND[0002]As is known in the art, dynamic random access memories (DRAMs) are used extensively in a wide range of applications. A DRAM typically includes an array of memory cells, each cell comprising an access transistor, typically a metal oxide semiconductor field effect transistor (MOSFET), coupled in series with a capacitor.[0003]A portion 10 of an array is shown in FIG. 1, which illustrates two complementary pairs of bitlines BL and BL′. While this figure only illustrates eight memory cells, it is known to fabricate DRAMs with millions of cells. Each bitline pair BL and BL′ is coupled to equalization / precharge circuitry and a sense amplifier, collectively labeled 12. Although not illustrated, many bitline pairs (and respective circuitry 12) are typically provided.[0004]Each memory cell includes an access...

AI Technical Summary

Benefits of technology

[0012]An advantage of a preferred embodiment of the present invention is a that single resist pattern can be used to expose portions of transistor gates as well as semiconductor substrate (e.g., source/drain regions). By replacing the nitride cap with an oxide layer for those transistors with gates to be exposed, these gates can be contacted while the gates of other devices remain protected.

[0013]This preferred embodimen

Problems solved by technology

This process is complicated in transistor designs that inclu

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